4 BIT RCA

AIM: Simulate, synthesize & implement the following combinational  and sequential designs using Structural description:

4-bit RCA using top down approach

Verilog code:

module struct_full_A(a, b, cin, sum, cout);

  input a, b, cin;

  output sum, cout;

  wire w1, w2, w3;

  xor G1 (w1, a, b);

  xor G2 (sum, w1, cin);

  and G3 (w2, w1, cin);

  and G4 (w3, a, b);

  or  G5 (cout, w2, w3);

endmodule

module rca_top_down(sum, cout, a, b, cin);

  input [3:0] a, b;

  input cin;

  output cout;

  output [3:0] sum;

  wire [3:0] c;

  struct_full_A fa_1(a[0], b[0], cin,  sum[0], c[0]);

  struct_full_A fa_2(a[1], b[1], c[0], sum[1], c[1]);

  struct_full_A fa_3(a[2], b[2], c[1], sum[2], c[2]);

  struct_full_A fa_4(a[3], b[3], c[2], sum[3], c[3]);

  assign cout = c[3];

endmodule

Test bench code:

module tb_rca_top_down();

   reg [3:0]a,b;

reg cin;

wire [3:0] sum;

wire cout;

rca_top_down DUT (sum,cout,a,b,cin);

initial begin

#10 a=4'b0000; b=4'b0000;cin=0;

#10 a=4'b0001; b=4'b0010;cin=0;

#10 a=4'b1010; b=4'b0101;cin=1;

#10 a=4'b1111; b=4'b1111;cin=1;

#20 $finish();

end

endmodule

OUTPUT: