MEALY MACHINE:

A Mealy machine is a type of Finite State Machine (FSM) in computer science where the output depends on both the current state and the current input, producing an output symbol during the state transition, unlike Moore machines where output only depends on the state. It's used in modeling digital systems, reacting quickly because its output changes immediately with input, often requiring fewer states than equivalent Moore machines 

VERILOG CODE 

module seq_detector_mealy (

    input clk,

    input rst_n,

    input x,

    output reg z,

     output reg [3:0] state,

    output reg [3:0] next_state

);

parameter A = 4'h1;

parameter B = 4'h2;

parameter C = 4'h3;

reg z_next;

always @(negedge clk or negedge rst_n) begin

    if (!rst_n) begin

        state <= A;

        z <= 1'b0;

    end

    else begin

        state <= next_state;

        z <= z_next;   

    end

end

always @(posedge clk) begin

    next_state = state;

    z_next = 1'b0;

    case (state)

        A: begin

            if (x == 1)

                next_state = B;

        end

        B: begin

            if (x == 1)

                next_state = C;

            else

                next_state = A;

        end

        C: begin

            if (x == 0) begin

                next_state = A;

                z_next = 1'b1;

            end

            else

                next_state = C;

        end

    endcase

end

endmodule

RTL SCHEMATIC:

POWER:

TIMING :