RANDOM COUNTER

VERILOG CODE:

module random (

    input clk,

    input reset,

    output reg [2:0] count

);

always @(posedge clk or posedge reset) begin

    if (reset)

        count <= 3'b000;   // starting state

    else begin

        case (count)

            3'b000: count <= 3'b101;

            3'b101: count <= 3'b011;

            3'b011: count <= 3'b110;

            3'b110: count <= 3'b001;

            3'b001: count <= 3'b000;

            default: count <= 3'b000;

        endcase

    end

end

endmodule

TEST BENCH:

module tb_random;

reg clk = 0;

reg reset = 1;

wire [2:0] count;

random dut (clk, reset, count);

always #5 clk = ~clk;

 initial begin

  #10 reset = 0;

  #100;

$stop;  // Stop simulation

end

endmodule