Theory :

The NAND gate (NOT-AND gate) is a universal gate formed by combining an AND gate followed by a NOT gate.

• 1. It has two or more inputs and one output.

  2. The output is the inverse (complement) of the AND operation.

  3. The output is LOW (0) only when all inputs are HIGH (1).

  4. In all other cases, the output is HIGH (1).

BLOCK DIAGRAM:

Boolean expression :

Y=A⋅B 

Verilog Code :

module NAND2_1(Y,A,B);

input A,B;

output Y;

assign y = (~(A&B));

endmodule

Test bench :

module tb_NAND2_1();

reg A,B;

wire Y;

NAND2_1 DUX(Y,A,B);

initial 

begin 

    A=1'b0 ; B=1'b0;

    #10 A=1'b0 ; B=1'b1;

    #10 A=1'b1 ; B=1'b0;

    #10 A=1'b1 ; B=1'b1;

    #20 $finish();

    end 

endmodule

OUTPUT:

 Pin Assignment: 

Input A = J15

Input B = L16

Output Y = H17