OPEN END

1.Aim : 

Simulate, synthesize & Implement the 4-bit ALU using only Multiplexers.

2.Theory : 

An Arithmetic Logic Unit (ALU) is the core component of any digital processor, responsible for performing both arithmetic operations (such as addition, subtraction, increment, and decrement) and logical operations (such as AND, OR, XOR, and NOT) on binary data. A 4-bit ALU operates on 4-bit inputs, providing outputs for a wide range of operations required in computing systems.

3.Verilog Code : 

// BASIC 2:1 MUX

module mux2(input a, input b, input s, output y);

    assign y = s ? b : a;

endmodule

// NOT USING MUX

module not_mux(input a, output y);

    mux2 m1(1'b1,1'b0,a,y);

endmodule

// AND USING MUX

module and_mux(input a, input b, output y);

    mux2 m1(1'b0,b,a,y);

endmodule

// OR USING MUX

module or_mux(input a, input b, output y);

    mux2 m1(b,1'b1,a,y);

endmodule

// XOR USING MUX

module xor_mux(input a, input b, output y);

    wire nb;

    not_mux n1(b,nb);

    mux2 m1(b,nb,a,y);     // XOR = (a?~b:b)

endmodule

// FULL ADDER USING MUX GATES

module fullAdder_mux(input a,input b,input cin,

                     output sum,output cout);

    wire axb,t1,t2;

    xor_mux x1(a,b,axb);

    xor_mux x2(axb,cin,sum);

   and_mux a1(a,b,t1);

    and_mux a2(axb,cin,t2);

    or_mux  o1(t1,t2,cout);

endmodule

// 4-BIT RIPPLE ADDER USING FULL ADDERS

module add4_mux(input [3:0] A,input [3:0] B,

                output [3:0] S,output Cout);

    wire c1,c2,c3;

    fullAdder_mux f0(A[0],B[0],1'b0,S[0],c1);

    fullAdder_mux f1(A[1],B[1],c1,  S[1],c2);

    fullAdder_mux f2(A[2],B[2],c2,  S[2],c3);

    fullAdder_mux f3(A[3],B[3],c3,  S[3],Cout);

endmodule

// 4-BIT BITWISE INVERTER

module invert4(input [3:0] A, output [3:0] Y);

    not_mux n0(A[0],Y[0]);

    not_mux n1(A[1],Y[1]);

    not_mux n2(A[2],Y[2]);

    not_mux n3(A[3],Y[3]);

endmodule

// 4-BIT SUBTRACTOR USING 2's COMPLEMENT

module sub4_mux(input [3:0] A,input [3:0] B,

                output [3:0] D,output Cout);

    wire [3:0] NB;

    wire [3:0] temp;

    wire c1;

    invert4 inv(B,NB);              // ~B

    add4_mux add1(NB,4'b0001,temp,c1);

    add4_mux add2(A,temp,D,Cout);   // A + (~B+1)

endmodule

// SIMPLE 4-BIT COMPARATOR

module comp4_mux(input [3:0] A,input [3:0] B,

                 output gt,output eq,output lt);

    assign gt = (A > B);

    assign eq = (A == B);

    assign lt = (A < B);

endmodule

// 8:1 MUX (4-BIT OUTPUT)

module mux8_4(

 input [3:0] D0,input [3:0] D1,input [3:0] D2,input [3:0] D3,

 input [3:0] D4,input [3:0] D5,input [3:0] D6,input [3:0] D7,

 input [2:0] S,

 output reg [3:0] Y);

 always @(*) begin

   case(S)

     3'b000:Y=D0;

     3'b001:Y=D1;

     3'b010:Y=D2;

     3'b011:Y=D3;

     3'b100:Y=D4;

     3'b101:Y=D5;

     3'b110:Y=D6;

     3'b111:Y=D7;

   endcase

 end

endmodule

TOP MODULE: 4-BIT MUX-ONLY ALU 

module alu4bit_mux(

 input  [3:0] A,

 input  [3:0] B,

 input  [2:0] S,

 output [3:0] F,

 output Cout);

 wire [3:0] wAND,wOR,wXOR,wADD,wSUB;

 wire addC,subC;

 wire gt,eq,lt;

 and_mux a0(A[0],B[0],wAND[0]);

 and_mux a1(A[1],B[1],wAND[1]);

 and_mux a2(A[2],B[2],wAND[2]);

 and_mux a3(A[3],B[3],wAND[3]);

 or_mux o0(A[0],B[0],wOR[0]);

 or_mux o1(A[1],B[1],wOR[1]);

 or_mux o2(A[2],B[2],wOR[2]);

 or_mux o3(A[3],B[3],wOR[3]);

 xor_mux x0(A[0],B[0],wXOR[0]);

 xor_mux x1(A[1],B[1],wXOR[1]);

 xor_mux x2(A[2],B[2],wXOR[2]);

 xor_mux x3(A[3],B[3],wXOR[3]);

 add4_mux AD(A,B,wADD,addC);

 sub4_mux SB(A,B,wSUB,subC);

 comp4_mux CP(A,B,gt,eq,lt);

 wire [3:0] GT = gt ? 4'b0001:4'b0000;

 wire [3:0] EQ = eq ? 4'b0001:4'b0000;

 wire [3:0] LT = lt ? 4'b0001:4'b0000;

 mux8_4 MUX(

   wAND,wOR,wXOR,wADD,wSUB,GT,EQ,LT,

   S,F);

 assign Cout =

      (S==3'b011)?addC:

      (S==3'b100)?subC:1'b0;

endmodule

4.Testbench Code : 

`timescale 1ns/1ps

module tb_alu4bit_mux;

    reg [3:0] A;

    reg [3:0] B;

    reg [2:0] S;

    wire [3:0] F;

    wire Cout;

    alu4bit_mux dut(

        .A(A),

        .B(B),

        .S(S),

        .F(F),

        .Cout(Cout)

    );

    task show;

    begin

        $display("T=%0t  S=%b  A=%b(%0d)  B=%b(%0d)  -->  F=%b(%0d)  Cout=%b",

                 $time, S, A, A, B, B, F, F, Cout);

    end

    endtask

    initial begin

        $display("\n====== 4-bit MUX-ONLY ALU TEST ======\n");

        A = 4'b0101;  B = 4'b0011;

        S=3'b000; #10; show();

        S=3'b001; #10; show();

        S=3'b010; #10; show();

        S=3'b011; #10; show();

        S=3'b100; #10; show();

        S=3'b101; #10; show();

        S=3'b110; #10; show();

        S=3'b111; #10; show();

        A = 4'b1010; B = 4'b1010;

        S=3'b101; #10; show();

        S=3'b110; #10; show();

        S=3'b111; #10; show();

        A = 4'b0000; B = 4'b0001;

        S=3'b011; #10; show();

        S=3'b100; #10; show();

        A = 4'b1111; B = 4'b0001;

        S=3'b011; #10; show();

        $display("\n====== Simulation Finished ======\n");

        $stop;

    end

endmodule