Verilog Code:

module cla4_df (

    input  wire [3:0] A, B,   // 4-bit operands

    input  wire Cin,           // carry-in

    output wire [3:0] S,       // 4-bit sum

    output wire Cout           // carry-out);

    wire [3:0] P, G;   // propagate and generate

    wire C1, C2, C3;   // internal carries

    // Propagate and generate

    assign P = A ^ B;

    assign G = A & B;

    // Carry logic

    assign C1 = G[0] | (P[0] & Cin);

    assign C2 = G[1] | (P[1] & G[0]) | (P[1] & P[0] & Cin);

    assign C3 = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & Cin);

    assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) | (P[3] & P[2] & P[1] & P[0] & Cin);

    // Sum

    assign S[0] = P[0] ^ Cin;

    assign S[1] = P[1] ^ C1;

    assign S[2] = P[2] ^ C2;

    assign S[3] = P[3] ^ C3;

endmodule

Test bench 

module tb_cla4_df;

    reg [3:0] A, B;

    reg Cin;

    wire [3:0] S;

    wire Cout;

    // Instantiate CLA

    cla4_df uut (A, B, Cin, S, Cout);

    initial begin

        // Test cases

        A = 4'b0000; B = 4'b0000; Cin = 0; #10;

        A = 4'b0001; B = 4'b0010; Cin = 0; #10;

        A = 4'b0101; B = 4'b0011; Cin = 0; #10;

        A = 4'b1111; B = 4'b0001; Cin = 0; #10;

        A = 4'b1010; B = 4'b0101; Cin = 1; #10;

        A = 4'b1111; B = 4'b1111; Cin = 1; #10;

        $finish;

    end

endmodule

OUTPUT:

RTL SCHEMATIC:

POWER:

UTILIZATION REPORT: