BEHAVIOURAL DESCRIPTION

VERILOG CODE 

module g_b_2(input [3:0]gray ,output reg [3:0]b );

always @(gray)begin

case(gray)

    4'b0000: b=4'b0000;

    4'b0001: b=4'b0001;

    4'b0011: b=4'b0010;

    4'b0010: b=4'b0011;

    4'b0110: b=4'b0100;

    4'b0111: b=4'b0101;

    4'b0101: b=4'b0110;

    4'b0100: b=4'b0111;

    4'b1100: b=4'b1000;

    4'b1101: b=4'b1001;

    4'b1111: b=4'b1010;

    4'b1110: b=4'b1011;

    4'b1010: b=4'b1100;

    4'b1011: b=4'b1101;

    4'b1001: b=4'b1110;

    4'b1000: b=4'b1111;

    default: b=4'b0000;

endcase

end 

endmodule

TESTBENCH 

module tb_g_b_2;

reg [3:0]gray;

wire [3:0]b;

g_b_2 dut(gray,b);

initial

begin

for(integer i=0;i<16;i=i+1)

begin

gray=i[3:0];

#1;

end 

$finish();

end

endmodule