MOORE MACHINE:

VERILOG CODE 

module seq_detector_moore (

    input clk, 

    input rst_n, 

    input x,

    output reg z,

    output reg [3:0] state, 

    output reg [3:0] next_state

);

parameter A = 4'h1;

parameter B = 4'h2;

parameter C = 4'h3;

parameter D = 4'h4;

always @(posedge clk or negedge rst_n) begin

    if (!rst_n)

        state <= A;

    else

        state <= next_state;

end

always @(*) begin

    case (state)

        A: begin

            if (x == 0)

                next_state = A;

            else

                next_state = B;

            z = 1'b0;

        end

           B: begin

            if (x == 0)

                next_state = A;

            else

                next_state = C;

            z = 1'b0;

        end

        C: begin

            if (x == 0)

                next_state = D;

            else

                next_state = C;

            z = 1'b0;

        end

        D: begin

            if (x == 0)

                next_state = A;

            else

                next_state = B;

            z = 1'b1;

        end

    endcase

end

endmodule

RTL SCHEMATIC:

POWER:

TIMING: