BEHAVIOURAL

Verilog code:

module bmux16_1(y, s, d); 

  input  [15:0] d; 

  input  [3:0]  s; 

  output reg y; 

  always @(s, d) begin 

    case (s) 

      4'b0000: y = d[0]; 

      4'b0001: y = d[1]; 

      4'b0010: y = d[2]; 

      4'b0011: y = d[3]; 

      4'b0100: y = d[4]; 

      4'b0101: y = d[5]; 

      4'b0110: y = d[6]; 

      4'b0111: y = d[7]; 

      4'b1000: y = d[8]; 

      4'b1001: y = d[9]; 

      4'b1010: y = d[10]; 

      4'b1011: y = d[11]; 

      4'b1100: y = d[12]; 

      4'b1101: y = d[13]; 

      4'b1110: y = d[14]; 

      4'b1111: y = d[15]; 

      default: y = 1'b0; 

    endcase 

  end 

endmodule

 Test bench code:

module tb_bmux16_1();

reg  [15:0] d; 

reg  [3:0]  s; 

wire y; 

bmux16_1 uut(y, s, d); 

initial begin 

$display("Select\tOutput"); 

$monitor("%b\t%b", s, y); 

d = 16'b0000000000000001;  s = 4'b0000; #10; 

d = 16'b0000000000000010;  s = 4'b0001; #10; 

d = 16'b0000000000000100;  s = 4'b0010; #10; 

d = 16'b0000000000001000;  s = 4'b0011; #10; 

d = 16'b0000000000010000;  s = 4'b0100; #10; 

d = 16'b0000000000100000;  s = 4'b0101; #10; 

d = 16'b0000000001000000;  s = 4'b0110; #10; 

d = 16'b0000000010000000;  s = 4'b0111; #10; 

d = 16'b0000000100000000;  s = 4'b1000; #10; 

d = 16'b0000001000000000;  s = 4'b1001; #10; 

d = 16'b0000010000000000;  s = 4'b1010; #10; 

d = 16'b0000100000000000;  s = 4'b1011; #10; 

d = 16'b0001000000000000;  s = 4'b1100; #10; 

d = 16'b0010000000000000;  s = 4'b1101; #10; 

d = 16'b0100000000000000;  s = 4'b1110; #10; 

d = 16'b1000000000000000;  s = 4'b1111; #10; 

#20 $finish; 

end 

endmodule