DATAFLOW

• Verilog Code:-

module RCA_4(

    input  wire [3:0] a, b,   

    input  wire cin,           

    output wire [3:0] sum,     

    output wire cout           

    );

    wire c1, c2, c3;

    assign sum[0] = a[0] ^ b[0] ^ cin;

    assign c1 = (a[0] & b[0]) | (b[0] & cin) | (a[0] & cin);

    assign sum[1] = a[1] ^ b[1] ^ c1;

    assign c2 = (a[1] & b[1]) | (b[1] & c1) | (a[1] & c1);

    assign sum[2] = a[2] ^ b[2] ^ c2;

    assign c3 = (a[2] & b[2]) | (b[2] & c2) | (a[2] & c2);

    assign sum[3] = a[3] ^ b[3] ^ c3;

    assign cout = (a[3] & b[3]) | (b[3] & c3) | (a[3] & c3);

endmodule

Test Bench:

module tb_RCA_4();

reg [3:0] a, b;

reg cin;

wire [3:0] sum;

wire cout;

RCA_4 uut(a,b,cin,sum,cout);

initial 

begin

    a=4'b0000; b=4'b0000; cin=0; 

#10 a=4'b0001; b=4'b0010; cin=0; 

#10 a=4'b0101; b=4'b0011; cin=0; 

#10 a=4'b1111; b=4'b0001; cin=0; 

#10 a=4'b1010; b=4'b0101; cin=1; 

#10 $finish();

end

endmodule

OUTPUT: