THEORY 

An asynchronous counter is a sequential circuit where flip-flops do not share the same clock; instead, the output of one flip-flop acts as the clock input for the next. In an asynchronous up counter, the toggling begins from the least significant flip-flop, and each stage triggers the next one when it transitions from 1 to 0, causing the overall count to increase. In an asynchronous down counter, the sequence moves in the opposite direction because each flip-flop is triggered by the opposite transition of the previous stage, causing the count to decrease. Because the clock ripples from one stage to the next, these counters suffer from propagation delay, making them slower and less accurate compared to synchronous designs, but they remain simple and easy to implement. 

BLOCK DIAGRAM:

WAVEFROM:

VERILOG CODE 

module asyn_down_cnt(q,clk,reset);

output reg [3:0] q;

input clk,reset;

always @(posedge clk or  reset )

begin

    if(reset==1)

        q = 4'b0000;

    else

        q = q - 1;

end

endmodule

TEST BENCH 

module tb_asyn_down_cnt();

wire [3:0]q;

reg clk,reset;

asyn_down_cnt dux(q,clk,reset);

initial begin

clk=0;

repeat(20)

#5 clk=~clk;

end

initial begin 

reset=1;

#20 reset =0;

#500 reset=1;

end 

endmodule

OUTPUT:

RTL SCHEMATIC:

POWER:

TIMING:

UTILIZATION REPORT:

GATE LEVEL DESCRIPTION:

VERILOG CODE 

module T_ff (

    input clk,

    input reset,

    input t,

    output reg q

);

always @(posedge clk or posedge reset)

begin

    if (reset)

        q <= 1'b0;

    else if (t)

        q <= ~q;

end

endmodule

module async_down_tff #(parameter N=4)

(

    input clk,

    input reset,

    output wire [N-1:0] q

);

genvar i;

generate

    for (i=0; i<N; i=i+1) begin: GEN_FF

        if (i == 0) begin

            T_ff FF (

                .clk(clk),

                .reset(reset),

                .t(1'b1),

                .q(q[i])

            );

        end

        else begin

            T_ff FF (

                .clk(~q[i-1]),

                .reset(reset),

                .t(1'b1),

                .q(q[i])

            );

        end

    end

endgenerate

endmodule

RTL SCHEMATIC:

POEWER:

TIMING: