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BLOCK DIAGRAM:

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VERILOG CODE 

module dff(q,qb,d,clk);

input d,clk;

output q,qb;

reg q=0;

reg qb=1;

always @(posedge clk)

begin

    q = d;

    qb <= ~q;

end

endmodule

TESTBENCH 

module tb_dff();

wire q,qb;

reg d,clk;

dff dux(q,qb,d,clk);

initial

begin

clk = 0;

repeat(10)

begin

    #5 clk =~clk;

end

end

initial

begin

d = 0;

#10 d = 1;

#10 d = 0;

#10 d = 1;

#20 $finish;

end

endmodule

RTL SCHEMATIC:

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