DATAFLOW

• Verilog Code:- 

module bcd_xs3(B3, B2, B1, B0, X3, X2, X1, X0);

input B3, B2, B1, B0;

output X3, X2, X1, X0;

assign X0 = ~B0;

assign X1 = ~(B1 ^ B0);

assign X2 = B2 ^ (B1 | B0);

assign X3 = B3 ^ (B2 & (B1 | B0));

endmodule

Test Bench:

module tb_bcd_xs3();

reg B3, B2, B1, B0;

wire X3, X2, X1, X0;

bcd_xs3 DUT(B3, B2, B1, B0, X3, X2, X1, X0);

initial

begin

    B3=0; B2=0; B1=0; B0=0;

#10 B3=0; B2=0; B1=0; B0=1;

#10 B3=0; B2=0; B1=1; B0=0;

#10 B3=0; B2=0; B1=1; B0=1;

#10 B3=0; B2=1; B1=0; B0=0;

#10 B3=0; B2=1; B1=0; B0=1;

#10 B3=0; B2=1; B1=1; B0=0;

#10 B3=0; B2=1; B1=1; B0=1;

#10 B3=1; B2=0; B1=0; B0=0;

#10 B3=1; B2=0; B1=0; B0=1;

#20 $finish;

end

endmodule

PIN ASSISSGMENT

> Input = J15

> Input  = L16

> Input = M13

> Input=R15

> Output = H17

> Output = K15
> Output=J13
> Output=N14