Theory : 

An OR gate is a fundamental digital logic gate that performs logical addition.

• 1. It has two or more inputs and one output.

  2. The output is HIGH (1) if any one or more inputs are HIGH (1).

  3. The output is LOW (0) only when all inputs are LOW (0).

BLOCK DIAGRAM

Boolean expression :Y=A+B 

Verilog Code :

module OR2_1(Y,A,B);

input A,B;

output Y;

assign Y = (A|B);

endmodule

Test bench :

module tb_OR2_1();

reg A,B;

wire Y;

OR2_1 DUX(Y,A,B);

initial 

begin 

    A=1'b0 ; B=1'b0;

    #10 A=1'b0 ; B=1'b1;

    #10 A=1'b1 ; B=1'b0;

    #10 A=1'b1 ; B=1'b1;

    #20 $finish();

    end 

endmodule

OUTPUT GRAPH: