Outlookに他人の予定表を表示させる方法を追加
http://rtcgroup.com/arm/2007/presentations/168%20-%20Formulating%20the%20Problem%20of%20Register%20Slice%20Optimization%20for%20AMBA%203%20AXI%20Bus.pdf
(register slice)
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features
- unidirectional data transfers
- multi master - multi slave (up to 16x16)
- TDATA byte widht conversion
- clock rate conversion
- configurable FIFO
- optional register slice
- multiple clock domains
overview
- large amount of data transfer
- derived from AXI3 write
- no address, response. non-deterministic burst
port signals
- TVALID
- TREADY
- TDATA(optional)
- TSTRB(optional)
- TKEEP(optional)
- TLAST(optional)
- TID(optional)
- TDEST(optional)
- TUSER(optional)
- Global
- ACLK/ARESETn
- ACLKEN(optional) ACLK enable
- Slave
- Snn_AXIS_****
- ACLK, ARESETN, ACLKEN
- TVALID (master driving valid transfer), TREADY(out)
- TDATA (payload) (in), TSRDB (size=TDATA/8)
- TKEEP (byte enable. size=TDATA/8)
- TLAST (the boundary of a packet)
- TID (size=ID)
- TDEST (routing information, size=TDATA)
- TUSER (size=TUSER)
(no "AXIS" in the name below)
- ARB_REQ_SUPPRESS (in) (skip this bus on the next arbitration cycle)
- DECODE_ERR (out. invalid TDEST)
- SPARSE_TKEEP_REMOVED, PACKER_ERR : not implemented (by Xilinx)
- FIFO_DATA_COUNT(32-bit) (out) write count in FIFO
- Master
- Mnn_AXIS_****
- ACLK, ARESETN, ACLKEN
- TVALID (master driving valid transfer), TREADY(out)
- TDATA (payload) (in), TSRDB (size=TDATA/8)
- TKEEP (byte enable. size=TDATA/8)
- TLAST (the boundary of a packet)
- TID (size=ID)
- TDEST (routing information, size=TDATA)
- TUSER (size=TUSER)
(no "AXIS" in the name below)
- SPARSE_TKEEP_REMOVED (out)
- PACKER_ERR : not implemented (by Xilinx)
- FIFO_DATA_COUNT(32-bit) (out) write count in FIFO
core switch
- switch data width
- parameters to arbitrate on TLAST boundaries
- optional pipeline stages
- programmable connectivity map
data width conversion (upsizer/downsizer)
master-slave connection with data widths of 8, 16, ... 4096
clock rate conversion
master/slave have different clock rates
register-slice (option)
datapath FIFO (option)
- 16,32, ..., 32768 deep
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burst length 1, 32/64 bit data, no exclusive
not supported signals: AxLEN,AxSIZE,AxBURST,AxLOCK,AxCACHE,xLAST
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difference from AXI3
AWLEN, ARLEN [7:0] <= [3:0]
AWLOCK, ARLCOK
AWCACHE, ARCACHE
WID (removed in AXI4)
Added
AWQOS, ARQOS
AWREGION, ARREGION
AWUSER, WUSER, ARUSER, RUSER
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IHI 0022B
channel VALID and READY
burst length 1-16
burst tr. size 8-1024(bits)
data bus width 8,16,...,1024
Write Address Channel
AWID[3:0]
AWLEN[3:0] burst length (AXI4 [7:0])
AWSIZE[2:0] burst size (bytes in each transfer in the burst)
3'b000 => 1, 3'b001 => 2, 3'b010 => 4, 3'b011 => 8
3'b100 => 16, 3'b101 => 32, 3'b110 => 64, 3'b111 => 128
AWBURST[1:0] burst type
Write Data Channel
WID [3:0] match AWID
WDATA[N-1:0] N is max 1024
WSTRB[M-1:0] M = N/4
Write Response Channel
BID [3:0] response ID
BRESP[1:0]
Read (skip)
Burst Length
AXI AxLength バースト長 +1が実際の長さになる (len=0なら1回)
AWLEN[3:0] burst length (AXI4 [7:0])
Burst Size
AWSIZE[2:0] burst size (bytes in each transfer in the burst)
2**ARSIZE
000 1 (1<<n)
001 2
010 4
011 8
100 16
101 32
110 64
111 128
Burst type FIXED(00),INCR(01)=address increment,WRAP(10)
xRESP[1:0] Response
----------------------------------------------------------------------
00 OKAY（通常のアクセスが成功した）
01 EXOKAY（排他的アクセスが成功した）
10 SLVERR（スレーブにアクセスが届いたけど、エラーを返した）
11 DECERR（デコード・エラー、インターコネクトでスレーブがそのアドレスにない）
Response OKEY(00),EXOKEY(01),SLVERR(10),DECERR(11)==decode error
ARLOCK Normal(00),Exclusive(01),Locked(10) AXI3
Normal(0),Exclusive(1)
LowPower
CSYSREQ,CSYSACK,CACTIVE
AWREGION?
AWUSER?
WUSER
BUSER
-
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master
+ write address
awvalid <= 1 @ (start req), <= 0 @ (awready & awvalid)
awaddr <= A @ (awready & awvalid)
+ write data (wnext = wready & wvalid)
wvalid <= 1 @ (start req), <= 0 (wnext & wlast)
+ wlast
burst: <= 1 @ (windex == last2 & wnext), <= 0 @ wnext
single: <= 1 @ , <= 0 @ (wlast && single)
windex count during (wnext & windex < blen-1 )
+ write response (B)
bready <= 1 @ (bvalid), <= 0 @ (bready==next cycle)
+ read address (same as write, replace aw with ar)
+ read data (rnext = rvalid & rready)
rindex count during (rnext & rindex < blen-1)
rready <= 1 @ (rvalid), <= 0 @ (next cycle)
rdata <= A @ (rnext)
+ resp error <= rresp[1] @ (rready & rvalid)
+ FSM
write burst end @ (bvalid & bready)
read burst end @ (rvalid & rready & rlast)
write transaction done @ (bvalid & bready & transaction count == max)
read transaction done @ (rvalid & rready & rindex == blen & transaction count == max)
slave
+ awready
awready <= 1 @ (awvalid & !(awv & awr) & !(arv & arr)), <= 0 (!wlast & !wready))
awv_awr <= 1 @ same as awready, <= 0 @ ( wlast & wready )
+ awaddr
latch of awsize/awlen/awburst.. @ (!awready & awvalid & !awv_awr)
latch of awaddr @ same as above
burst increment @ ((cnt > 0) & wready & wvalid)
burst inc/wrap depending on awburst
+ wready
wready <= 1 @ (wvalid & awv_awr), <= 0 @ (wlast & wready)
+ write response (B)
bvalid <= 1 @ (awv_awr & wready & wvalid & ~bvalid & wlast )
<= 0 @ (bready)
+ read
arready <= 1 @ (arvalid & !awv_awr & !arv_arr)
arv_arr <= 1 @ same as above, <= 0 (rvalid & rready & arlen_cnt = 0)
arready <= 0 @ ..
+ araddr
latch @ (!arready & arvalid & !arv_arr)
arlast <= 1 @ (arlen_cnt=0 & !arv_arr), <= 0 @ rready
+ rvalid <= 1 @ (arv_arr) , <= 0 @ (rready)
+ address <= A @ arv_arr | awr_awr
wren <= wready & wvalid, rden <= arv_arr
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PCKJ _|~|_|~|_|~|_
PSEL ____/~~~~~~\
PWRITE ____/~~~~~~\
PENABLE ________/~~\
PREADY ________/~~\
(from slave)
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APB: second and subsequent cycles for transfer
Ready
APB: (S)slave uses this signal (slave outputs)
AXI: (S)slave is ready to accept signals
(M)master can accept response
Valid
AXI: (M)signaling valid address
(S)response is valid
(APB: PSEL corresponds it, OCP: so does Cmd)
Response(S)
AXI: status of transaction
OCP: response data
Accept
OCP: (S)command accept, data accept(when issues of cmd and data are in different timing)
Req
Ack
Request is accepted correctly. (Nack: incorrectly)
Grant
DMAC is granted controll of system bus.
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xRESP[1:0] Response
----------------------------------------------------------------------
00 OKAY（通常のアクセスが成功した）
01 EXOKAY（排他的アクセスが成功した）
10 SLVERR（スレーブにアクセスが届いたけど、エラーを返した）
11 DECERR（デコード・エラー、インターコネクトでスレーブがそのアドレスにない）
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AHB HRESP
00: OK, 01: ERROR, ...
HTRANS 0:IDLE, 1:BUSY, 2:NOSEQ, 3:BURST
HBURST 0:SINGLE, 1:INCR, 2:WRAP4
Output HADDR,HSEL,HWDATA,HWRITE
Input HREADY,HRESP
Burst beat(size) と length
beat は一回の転送の塊
lengthはその回数
INCR はアドレスが増えていく。一番直観的なバースト転送
FIXEDはアドレス固定？ WRAPは?
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Handshake Valid -> Ready
5 channels (Read Address, Write Address, Read Data, Write Data, Write Response (B) )
QoS 優先順位と考えてよい。0から15で数値が大きいほど調停で優先される。
AXIではチャネルごと(AR,AW)に設定できる
Outstanding 前の転送前にリクエストを投入できること。投入された数が Outstanding数
WSTBRS Write Strobes
どのバイトレーンを更新対象とするか
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ARM Interconnect? NIC? で AXI->APB があるとき、
かつ APB のクロックがAXIより遅いとき、
clock enable で aclk をストロボする必要がある
（理由の説明は間違ってるかもしれんが、必要なのは間違いない）
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AXI + hw coherent cacher