PRELIMINARY DRAFT. May contain errors. Has not been verified by me yet.
Overview
This refers to the EH 7550 schematic, or models having EH1307 circuit board designation. From the outside, these are the "4 knob" Deluxe Memory Man pedals with "Squelch" slide switch.
These pedals contain 4 Reticon SAD1024 dual delay chips. 4 dual chips = 8 delay stages. 8 delay stages means you've got a lot of inputs and outputs to check! (For comparison, the 5 knob Deluxe (EH 7850) is much simpler to calibrate, as it only contains 2 MN3005 chips, and each chip only has 1 stage of delay.) Each chip has 2 trim pots, so there are 8 trims total. 4 trims are for bias. Each chip must be biased with a steady dc voltage that allows for minimal signal distortion. 3 trims fine tune the output level of the first 3 chips. The final trim is for cancellation of the clock signal.
Initial Setup
Inject a audio test signal, sine wave, low distortion. Howard Davis' EH7850 calibration recommends to start with 250Hz and 500mVp-p. Neither of these are critical - use whatever mid range frequency is convenient, and signal can be less than 500mVp-p. (Note the delay signal frequency response scope photo on the memory man main page. You want the signal to be in the pass band.) The signal is boosted at the "Level" control before hitting the delay chips. Signal "overload" LED should not be illuminated. The ideal input to the delay chips is the max without clipping. What that exact p-p voltage level is, I do not know at this time.
Make sure feedback is at minimum (off) when trying to calibrate. The performance of each SAD1024 degrades as slower clock speeds (longer delay times) are used. I think the 7850 calibration recommends to start at 50% delay time, and then check again at fully CW and CCW. If you hear a high pitched whine at long delay times, even after you think it's well calibrated, you may simply have too slow a clock speed. Check the clock speed - it is probably dipping well into the audio band (<20kHz, long delay time might have a 10kHz or less clock rate) and you are simply hearing it superimposed on the audio. If shorting the delay time fixes this issue, then you should go into the RC network attached to the delay control and adjust the minimum clock time to prevent the clock whine.
IC4
First delay stages is IC4. There are two delay stages on IC4, one on each side of the chip. The two stages are directly connected together, and share a single bias trim pot (VR1). First input is pin 15, output is both pins 11 & 12. This output goes to input pin 2, and the next output is pins 5 & 6. Observe each output pair, switch back and forth, with the oscilloscope while adjusting the trim. Adj for the lowest distortion output. You should see obvious distortion as you move the bias trim away from the sweet spot. One of the difficulties of the SAD1024 Memory Man design is how 2 stages share the same bias trim. If you calibrate stage 1, then stage 2, stage 1 might now be off! So you have to check both.
Another difficulty here is that you will see a lot of clock signal superimposed on the audio signal, and this makes the image blurry on the oscilloscope. If you can make a little low pass filter between the scope probe and the oscilloscope input, this can help. This can be as simple as a single resistor and a capacitor. Or you can just try to ignore the blurry image.
Note that output of IC4, pins 5&6 (stage 2) is connected to VR5, an attenuator trim. If you have this set too low, you won’t see any output. The first 3 SAD1024s have 1 attenuator trim (labelled "gain" on the schematic) at the 2nd output. I am not sure on the best order to calibrate the attenuators - read on, and we’ll revisit them. At this point, just be sure that none of them are fully off, and try to keep the inputs and outputs at about the same level. Ultimately we want the original input and the final output to match.
IC5
Next is chip IC5. Input is 15, output 11 & 12, directly goes into pin 2, output 5 & 6. Both stages share bias trim VR2. Same as before, you have to check both output pairs while adjusting the trim, switch back and forth and make sure both are coming through clean.
You can adjust VR5, that attenuator trim, to lower the input signal if needed.
VR6 is the output attenuator for this second group in IC5.
This is the 1/2 way point, and the delay goes through IC6A, inverting amplifier.
IC7
IC7 is the next group of two delay stages. Pins are the same as before. VR3 is your bias. Adjust like the previous stages. Use VR6 to lower the signal coming into IC7.
VR7 is the output attenuator.
IC8
Next is IC8. Bias is VR4. Check output for distortion. Use VR7 if you need to lower the input.
Finally, VR5 is the “Balance” trim. This is to cancel the clock noise. You will not 100% cancel the clock noise. You just want to minimize it. You can observe the scope at the wiper of the trim pot (without the filter, if using one). A low pass filter follows this (IC6B and IC4B) to remove the remainder of the clock noise.
Setting the delay level
Back to the attenuator trims: I believe you should end up with the same level of signal at the input as you get at the output, and the output trims are there is correct this along the way. But then there is IC6A section, which I cannot even clearly read the resistor values on the schematic, but that appears to be an additional attenuation. It will be clearer to me when I have a real unit on the bench again, and I will update this at that time.
Looking at the 1977 SAD1024 datasheet, page 2 shows a chart that indicates unity gain when the output has a 4k load, and the output can get up to at least x1.2 at higher output loads.