Bucket Brigade Delay

History of solid state delay units for audio.

Bucket Bridge Delay is a long series of Sample and Hold

The BBD chip is really just a LOT of MOSFETS lined up in a row. The basic series path is arranged like any FET audio switch (see how a BOSS bypass works, for instance) where the audio passes from drain to source when the gate is ON and the audio is blocked when gate is OFF.

In addition to the FET switches, there are capacitors between each FET to “sample and hold” (S/H) the audio voltage. So it’s not just MOSFETS. Updating the first statement, now we have: the BBD chip is a LOT of sample/hold circuits lined up in a row.

In order for this train of S/H circuits to reproduce audio, the sampling has to be really fast. It must be sampling faster than the signal audio (~20kHz is the fastest audio) or else it isn’t going to work correctly. The high frequency response of BBD chips is limited because of this and the fact that the S/H capacitors also function as a low pass filter just as an inherent property of capacitors.

The SAD1024 is a BBD IC by Reticon with dual 512 stage sections. (1024 stages total.) SAD is an acronym for "serial analog delay." This IC was definitely available by 1976, with anecdotal/alleged reports of a 1975 release. The original Memory Man line used the SAD1024 and is alleged to have been made available in 1976.

The MN3005 is a BBD IC by Panasonic with 4096 stages of S/H. The Memory Man line switched to the MN3005 chips perhaps around 1978, judging by the dates on the factory schematics for EH-7810 and EH-7850.

The MN3001 appeared in November 1974. The MN3001 is a dual 512 stage BBD, like the SAD1024.

MN3002 is a single 512 stage IC featured in the 1975 Roland Jazz Chorus and the 1976 Boss CE-1.

The Reticon single 512 stage IC is the, you guessed it, SAD512.

Confusion regarding SAD, BBD, CCD, and CTD

Reticon also used the term SAD (serial analog delay) as any circuit block that performed analog delay, so it also appears when discussing Reticon CCD chips. For instance, the R5101 2000 stage CCD is said to have a 2000 stage SAD in the Reticon literature. This causes confusion if someone has "learned" that anything "Reticon + SAD" = BBD. The term SAD can refer to BBD or CCD Reticon circuits, but they are different technologies, with different strengths and weaknesses, but with similar end results when used as an analog delay. (i.e. Reticon wasn't "confusing" or arbitrarily swapping the terms around.) BBDs and CCDs are both CTDs, which stands for "Charge Transfer Devices."

CCDs were the superior technology and they were developed into digital photography electronics even during the heyday of '70s analog delays. Because many engineers and electronic hobbyists think of CCDs as digital photography devices, there seems to be some confusion out there as to how a digital photography chip can be used for analog audio delay. In this case, the thinking is backwards. CCDs started out as chains of S/H just like BBDs. The audio delay application is a rather pedestrian application of the technology, and the results for straight delays are mediocre compared to a good digital delay. Vintage effect aficionados may appreciate the mediocre performance as "tone," but the greater population accepted digital delay as superior in the 1980s, and that was the end of the original CTD analog delay era.

Most BBDs require two out-of-phase clock signals

Sampling rate is determined by a clock signal, usually generated externally and connected to pins on the BBD IC. The clock pins drive the gates of the MOSFETs, providing the necessary ON/OFF signals. Early (c. 1968) BBD attempts only had one clock. You may have noticed that all the BBDs you encounter have 2 clocks, and if you’re really observant, the 2 clocks are 180 deg. out of phase. Why did BBD manufacturers end up with the 2 clock system? The technical evolution can be found in some "white papers" from Reticon by Buss and Weckler. Skipping the deep electronic technical hurdles, the 2 clocks, being out-of-phase, can be cancelled at the output, removing the bulk of the unavoidable "clock noise," while the two signals are summed in-phase.

The cancel effect is usually achieved with a trimpot. This is the "cancel" trim. The CW and CCW ends of the pot are connected to OUT 1 and OUT 2, and the summed output is the trim’s wiper. Any time you see this trim (easy to identify), you can always just observe the wiper terminal and adjust for maximum cancellation. Do not expect the clock signals to perfectly cancel. You will adjust for minimum clock signal and that's it. The audio signal will still have a lot of jittery looking clock noise at the best "cancel" trim setting. Removal of this last bit of clock noise has to be achieved via low pass filtering in the next stage.

The clock signals are generated by a CD4047 timer IC for Memory Man pedals.

MXR, DOD, and others use a CD4013 dual flip flop driven by an oscillator.

Roland/Boss used discrete BJT flip flops driven by an oscillator, CD4013 driven by an oscillator, and MN31XX clock driver ICs.

Some BBD chips even include the clock driver circuitry inside the same IC. These chips must have been expensive, because guitar effect makers seemed to ignore them.

CCD chips require a more complicated multiphase clock.

The inputs need a bias voltage

The other required trim is the "bias" trimmers. Any FET being used as an audio gate needs to be preset to some voltage that allows the audio to swing both above and below the quiescent voltage. The quiescent voltage in the audio path is called the "bias voltage," and it is set with a trimpot usually, but on some designs the trim will be eliminated (the voltage will still be applied through some resistive path). The bias trimmers can be identified as coming from the power supply and delivering a “bias voltage” to the inputs of the BBD chips. Sometimes there is one bias trim per input, and sometimes multiple inputs will share a single bias trim. Since the bias of each stage has a direct effect on the final total harmonic distortion (THD), more trims allow for dialing in the best distortion figure at the expense of increased calibration time and parts.

The BIAS trim is adjusted by monitoring the output of the input you are adjusting. Adjust for best looking signal, i.e. good/max amplitude without distortion, and double check this throughout the sweep of the DELAY TIME panel control. There is usually only a very fine section of the trim pot that will allow the BBD to function. Moving too far CW or CCW will turn off the BBD entirely. Sometimes a “dead” chip simply has a wrong or missing bias voltage on the input. Once the bias trims have been set by ear or with the scope, a fine tuning can be achieved with a THD meter. I monitor the final output and tweak each bias trim until the lowest possible THD figure it achieved. The THD figure will go up and down with frequency, so check low, mid, high, and just try to keep the average as low as reasonably possible. This step is really only for the perfectionist. For typical use, setting the bias trims by ear is good enough.

Power Supply Requirements

The original BBD devices from Reticon and Panasonic suggested a 15V power supply plus a slightly lower (1V) power supply for the gates. Additionally, the Panasonic chips specified that the voltage be negative, and labeled the Vdd max rating at -15V. This implies you need a -15V power source, but that is not true. It is simply a P-Ch FET device, which means that Vss will be more positive than Vdd. So if Vdd = 0V, Vss can be +15V, or +9V. A lower supply voltage simply reduces headroom and therefore your max theoretical signal-to-noise ratio. If you glance through the schematics for various BBD based delays, you will note that while the Electro Harmonix Deluxe Memory Man used an actual -15V power supply, other companies simply used a positive supply to Vss and 0V at Vdd.

The MN3000, P-Ch, series was followed by the MN3200 series, N-Ch devices. Voltages are given as positive voltages for Vdd. The max voltage Vdd voltage is listed as +10V for all the MN32xx chips. The MN3200 series was specifically designed to meet the demand for battery operated delay devices (it says as much in the Foreward of my hardcopy of the Panasonic datasheet book).

Can I substitute some other chip for my dead SAD1024/MN3005?

Short answer is, "yes," with the caveat that it is not simple to do, and do not try to simply plug something else in a socket. A typical solution is to make a plug-in daughterboard to adapt the new chip to the old chip's footprint. The SAD1024 based Memory Man pedals use the dual 512 delay stages in series, effectively making them 1024 stage BBDs. The MN3007 is a single 1024 stage BBD than can be adapted to replace a serial connected SAD1024. MN3007 chips are still reasonable priced (a few dollars per chip as of 2015). The MN3005 is a single 4096 stage BBD. 4x MN3007 can be adapted to replace a MN3005. More combinations than these are possible. It would be dictated by what you need replacing, and what chips are available at the time you look for them. (i.e. if you stumbled across a trove of single 512 stage chips for $0.01 each, you could use 8 to replace a 4096 stage chip, 2 to replace a dead 1024 stage chip, etc ...)

At this time, I have no experience in actually creating these types of plug-in boards. I have only seen many threads on the subject at forums like diystompboxes, freestompboxes, etc. I have definitely seen at least one layout for a plug-in board on freestompboxes. You probably have to sign up and become a member to view the file. As a repair person, the labor costs to make such daughterboards usually outweighs the cost of simply purchasing a $50-$75 SAD1024 on eBay.