Common Emitter with Series Feedback
Design Example
Disclaimer: This is just a illustrative example to show one approach to designing this type of circuit. I do not purpose this to be the best way, or even a "correct" way to do it. It does work for me and maybe it will work for others.
Our purpose with this circuit is to amplify an input voltage connected at C1 into a useful output voltage at C2.
The amplification is going to result from a small voltage change at the base of Q1 controlling a large voltage change at the collector of Q1. Will will assume the transistor's hfe is 100 or more.
We can roughly set the voltage gain by the ratio of the collector resistor value to the emitter resistor value. So, for instance, if we want a 10:1 gain, we might try a 10k collector resistor and a 1k emitter resistor.
We still need to figure out the values for R1 and R2. These resistors will create a circuit that biases Q1 into a forward active state. To maintain the correct operating point, a certain degree of stability is required, and our R1 and R2 resistors must be low enough in value to provide stability. However, the input signal will be attenuated if R1 and R2 are too low. For maximum input voltage transfer, we want R1 and R2 to be high value. We have conflicting goals, so some sort of compromise has to be reached.
To actually calculate our values, we need to first decide what our target quiescent (no signal) collector voltage is. Typically this is 1/2 of the supply voltage for maximum swing. That means our target will be a collector voltage of 4.5V with a 9V supply.
Using Ohm's Law, we can now estimate the current that will be flowing through the collector resistor if the collector voltage is 4.5V.
IC = 4.5V / 10kΩ = 4.5V / 10,000Ω = 0.00045A = 450µA
We can assume that the REmitter will have a current that is roughly equal to the collector current plus the base-emitter current. For simplicities sake, we'll ignore the base-emitter current, since it will be small compared to the emitter current.
These assumptions allow us to figure out the emitter voltage.
VE = (450µA) * (1kΩ) = (0.00045A) * (1,000Ω) = 0.45V = 450mV
We will now assume that Q1 is silicon and has a 600mV base-emitter forward voltage drop. Since we assume VE = 450mV, we simply add the base-emitter drop to figure out the base voltage.
VB = 0.6V + 0.45V = 1.05V
We still haven't touched the R1 or R2 values, but we now have enough information to calculate for them.
Intuitively, you should see that in order to have about 1V appear at the base, from a 9V supply, R1 is going to be much larger than R2.
We don't want either resistor to be too small, and thus heavily attenuate our input signal, so we'll start with the smaller of the two: R2.
Our 1k emitter resistor "looks like" a 100k resistor due to the transistor's multiplying effect from base circuit to collector circuit (assuming hfe ≥ 100). We want R2 to be large enough to not attenuate the input, but we want it smaller than the 100k input impedance to the transistor base for stability.
For simplicity in this example, we'll choose 10k for R2. This will be plenty stable against the 100k input impedance of Q1, and a line level, buffered signal should be able to drive the 10k || R1 resistors.
But what is R1? Here we pull out our voltage divider calculations.
We can calculate R1 this way:
R1 = ((R2 * Vin) / Vout) - R2
R1 = ((10k * 9V) / 1.05) - 10k
R1 = (90,000 / 1.05) - 10k
R1 = 85,714 - 10,000
R1 = 75k
We can now calculate an estimate for the input impedance of Q1 with the R1/R2 divider network, as:
Zin = R1 || R2 || (RE * beta)
Zin = 10k || 75k || 100k
Zin = 1 / (1/10k + 1/75k + 1/100k)
Zin = 1 / (0.0001 + 0.000013 + 0.00001)
Zin = 8k
C1 and C2 couple the ac signal to the previous and following stages, respectively, while blocking the dc voltage. Ideal capacitors have an infinite impedance at low frequencies (i.e. dc) and a low impedance at high frequencies. They make natural high pass filters when used in series with a voltage signal. Here, we can either make C1 and C2 sufficiently large so as to have little to no high pass filter effect on audio signals, or we can purposefully make them smaller to attenuate the bass.
We start with the usual capacitor filter calculation:
f-3dB = 1 / (2πRC)
But we switch it around to solve for the capacitance at a desired cutoff frequency.
C = 1 / (2πRf-3dB)
Note that the frequency you solve for will have some attenuation, so you may want to solve for a bit lower frequency than you want unattenuated.
Let's just choose the bottom end of human hearing, roughly 20Hz, and solve for the input impedance.
C1 = 1 / (2π * 8k * 20Hz)
C1 = 0.000 000 994 718
C1 = 0.000 001 (rounding)
C1 = 1µF
For the output impedance, we have to guess, because C2 is going to form a voltage divider with the following stage's input impedance. Since we have a relatively high output impedance of 10k, our next stage shouldn't have an input of less than 100k, so we will solve for 100k.
C2 = 1 / (2π * 100k * 20Hz)
C2 = 0.000 000 079 577
C2 = 0.000 000 100 (rounding)
C2 = 100nF
I threw this in a SPICE simulation and added 1k source resistance, which is a common real world output impedance from a previous stage. I got a gain of about 7.7 at 1kHz.
This has been just a illustrative example to show one approach to designing this type of circuit. I do not purpose this to be the best way, or even a "correct" way to do it. It does work for me and maybe it will work for others.
As a next step, try starting over with a desired gain of x3. This will reset the initial collector and emitter resistors.
Try building these circuits on the breadboard and measure the actual gain you get. Does it match the theory or do you need to tweak your values to hit the desired gains?
Compare frequency responses with different capacitor values. You can either some kind of sweep tone generator or just plot individual frequency inputs. You can use broad strokes like octaves and decades, or narrow in on the low end to see the effect of moving C1 and C2 up and down.
The actual Q1 voltages will depend upon the transistor's beta, but making R1 and R2 low impedance compared to the Q1 input impedance will minimize the influence from the beta parameter. Try raising R1 and R2 (raise R2 arbitrarily, then recalculate R1 to keep the ratio the same) and note the effects on the circuit. Many practical designs have rather high R1 and R2 values when input impedance is more important than circuit stability. If our dc voltages shift a little, we probably won't notice in a simple guitar distortion circuit, but we may notice a loss of treble if our input impedance is too low.
Eliminating the series feedback with a capacitor
The emitter resistor has no bypass capacitor in this example. Adding a large capacitor in parallel to the emitter resistor will leave the dc biasing alone while lowering the ac impedance of the emitter circuit. This has the effect of both lowering the signal input impedance, and raising the overall voltage gain. The gain is boosted because we are removing the series negative feedback at signal frequencies that normally develops across the emitter resistor.
Understanding the series negative feedback and how it can be eliminated with a capacitor is key to understanding how the 2 Transistor English Fuzz "fuzz"/gain control works.