b. International Symposium on IoT Enabling Chips

International Symposium on IoT Enabling Chips

June 20 (Sat.) 10:15 - 17:35 (Open XX:XX)

Matsugasaki, Sakyo-Ku, Kyoto, 606-8585 Japan

Scope

In the International Symposium on IoT Enabling Chips, state-of-the-art chip designs covering the wide range of IoT including the data centers and sensory IoT swarms are presented by the world-leading experts to provide an opportunity for VLSI engineers to understand the leading-edge trend of “IoT Enabling Chips”. There are three sessions. In the first session, high-speed and power-efficient serial links and new computing chips in the data centers are presented. In the second session, automobile and medical applications, and nW-circuits for mm³-scale IoT swarms are shown. In the last session, key building blocks for IoT including the embedded power management for energy efficient operations and an attack resistant cryptographic engine are shown.

Program

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Organizing Committee Members

General Chair: Toshiro Hiramoto (University of Tokyo)

Program Chair: Makoto Takamiya (University of Tokyo)

Program Vice Chairs: Masayuki Mizuno (Renesas Electronics), Hirokazu Sugimoto (Panasonic Semiconductor Solutions)

Local Arrangements: Kazutoshi Kobayashi (Kyoto Institute of Technology)

Secretaries: Takahiro Shinada (Tohoku University), Hiroshi Kawaguchi (Kobe University)