11月国際シンポジウム
International Symposium on Advanced Silicon-based Nano-devices (ISASN)
2007/11/9(Fri)
Toranomon Pastral , Tokyo, Japan,
Japanese Version
Sponsored by
"Ultimately Integrated Devices and Systems" Research Committee (165 Committee) in the Japan Society for the Promotion of Science
Co-Sponsored by
IEEE Electron Devices Society (EDS) Japan Chapter, The Global COE Program "Center for Electronics Devices Innovation", Graduate School of Engineering, Osaka University
Scope & Summary
Performance of Si-VLSI circuits have been drastically improved year by year and the technology has become indispensable for current advanced IT society. MOSFETs, which are the main components of the LSIs, have been scaled down ultimately to nano-size in order to meet the performance improvement of LSIs. However, in that regime, we face several new issues on nano-physics and are requested to control and design those nano-devices, based on the understanding of the new phenomena.
Therefore, the aim of the International Workshop on Advanced Silicon-based Nano-devices is to invite distinguished researchers of this field in and out of Japan and discuss the scaling related issues and their possible solution technique. We hope the introduction of up-date research results and intimate discussion would lead to vision of nano-scaled LSIs as well as future society which will be realized with the technology.
Conference Venue
Conference Venue is Toranomon Pastoral. See Here for detail.
Registration
Registartion fee is 5,000 JPY (including Proceedings, Coffee Break, and Banquet). If you can read Japanese, please go to the registration site. Otherwise, please contact with the secretariat (intws07@vlsi.kuee.kyoto-u.ac.jp)
Final Program of International Symposium on Advanced Silicon-based Nano-devices
9:00-9:05
Opening Remarks: Prof. Kenji Taniguchi (Osaka University)
Session 1
Toward the Ultimate Scaling and Si NW Electronics
9:05-9:50
Prof. Asen Asenov (University of Glasgow), " Simulation of Atomic Scale Statistical Variability in Nano-CMOS Using DD, MC and QT Techniques "
9:50-10:35
Dr. Supratik Guha, (IBM), "Semiconductor Nanowire Devices and Doping Behavior"
10:35-10:50
Break
10:50-11:35
Dr. Donggun Park (Samsung Electronics), "Silicon Nanowire CMOSFETs: Fabrication, Characteristics, and Memory Application"
11:35-12:20
Prof. Guo-Qiang Lo (Institute of Microelectronics, Singapore Science Park-II), "Si/SiGe-Nanowire Technology Platform and Devices Applications based on Top-Down Approach"
12:20-13:20
Lunch Break
Session 2
Alternative Channel Devices
13:20-14:05
Prof. Shinichi Takagi (University of Tokyo, MIRAI-AIST), "High Performance CMOS Device Technologies using New Channel Materials"
14:05-14:50
Prof. Iain Thayne (University of Glasgow), "III-V MOSFETs for Silicon Co-Integration"
14:50-15:10
Break
15:10-15:55
Prof. Suman Datta (Penn State University), "Prospects of Ultra-High Mobility Narrow Gap Semiconductor Quantum Wells for Very Low-Power Logic Applications"
15:55-16:40
Prof. Shinjiro Hara (Hokkaido University), "III-V Semiconductor Nanowires and Their Device Applications"
16:40-16:45
Closing Remarks: Prof. Toshiro Hiramoto (University of Tokyo)
17:00-19:00
Banquet
Committee
Program/General Co-Chairs
T. Hiramoto (Univ. of Tokyo), A. Nishiyama (Toshiba)
Secretaries
K. Kobayashi (Kyoto Univ.), M. Takamiya (Univ. of Tokyo)
Previous Symposiums
- International Symposium on Advanced Reconfigurable Systems (2005/12)
- International Symposium on Advanced Si-RF LSI Circuits and Devices (2004/12)
- International Symposium on Advanced Devices and Process Technology (2003/11)
Contact
If you have any questions, please contact the sectretary ( intws07 at vlsi.kuee.kyoto-u.ac.jp)
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