Below is a proposal for a microcontroller based UART for limited, low speed communication between microcontrollers. In this case, the communication will be between a Raspberry Pi (master) and an Arduino (slave).
Interface:
Three wire interface
Power
Ground
Data
Power is +5 volts - common to both Pi and Arduino power usage
The data line is preferred to be an open collector line pulled to 3V (input voltage limit for the Pi). However - the driving device for a given data block may drive the line high/low, while all other devices listen to the line. The protocol defines that there should be a single, specific master within the set of devices. It will initiate communication, then go into listen mode until one slave responds. The protocol specifies that data will be transferred in byte pairs (with additional overhead bits) - one byte providing address, the second byte being data sent or received. If the master is sending data, it may send an address byte, followed by a data byte. It may then send an address byte and expect the slave to echo or ack the previous transaction to verify.
Multiple devices supported. Single master. Many slaves may be connected to the single data line. Each slave must have a unique address to prevent contention.
The protocol is "asynchronous", but will send a timing pulse with every data pair packet. The receiving device(s) may measure the timing pulse to allow timing of the rest of the bits. This will allow the data speed to be changed on the fly, although that is not the intention. More importantly, it removes the restriction of having an accurately calibrated internal clock, as long as all devices can count / measure / time the length of the timing pulse.
Data Exchange Packet Timing:
The common timing concept of a "clock period" will be used in this description. The "clock" is strictly an internal reference for timing purposes. The "clock" is assumed to have a high and low portion of equal time. Data will always be sampled halfway through the clock period.
Data line defaults to floating high.
ATTN (Attention) pulse: Data line pulled LOW. This pulse may be of any duration, but should typically be of one clock period (high and low clock pulse).
Data line floats high for one clock period.
TIMING PULSE: Data line is pulled low for a total of 4 clock cycles (4 entire high and low phases). All slave devices will measure this timing pulse, and use the time they measure to be the reference for the rest of the data exchange.
Data line floats high for one clock period.
8 Address bits sent - The top 7 bits are the actual address. The most significant address bit is sent first. The lowest bit of the byte is set to 1 for a READ from slave operation, set to 0 for a WRITE* to slave operation. Each bit is asserted on the data line for a full clock period (time of a full high and low clock phase). Data should be read by each slave device at the mid point of the assertion.
Data line floats high for one clock period.
For READ Operations:
The addressed slave will respond by sending 8 data bits, MSB sent first. Each bit will be asserted on the data line for the duration of a clock period. The data bit will be sampled by the master at the midpoint of the clock period.
For WRITE Operations:
The master will send 8 data bits, MSB sent first. Each bit will be asserted on the data line for the duration of a clock period. The data will be sampled by the addressed slave at the midpoint of the clock period.
Data line floats high for one clock period.
ACK bit - The addressed slave will assert the data line LOW for one clock period. The master will sample the data line at the midpoint of the clock period. If no ACK assertion is made on the data line, the master will assume that either there was no slave device with the indicated address, or that the data transfer failed.
Data line floats high for at least 2 clock periods before next transfer may begin.
Misc. Details:
Address 00 is reserved as a special address that the master may use to broadcast to all slave devices. Use of this address requires that all slave devices must be open collector for the ACK bit, or that none of the slave devices returns an ACK bit to the Address 00.
Address 7Fh is reserved as a special address for all slaves to respond in unison. Use of this address requires that all slave devices must be open collector to prevent contention.