Reservoir computing has recently attracted attention as a AI computation method with computational load for learning. We have recently proposed that ferroelectric gate MOSFETs (FeFETs) and FeRAMs with memory-in-logic and nonlinear analog computing functions are promising hardware for physical implementation of reservoir computing. Also, we have demonstrated its reservoir computing operation for the first time in the world. Using these reservoirs based on ferroelectric devices, we are conducting research to realize new AI hardware on Si platforms that can perform inference and learning with extremely low power consumption.

3D-integrated CMOS, in which transistors are vertically stacked, is expected to be a key device for future logic LSIs. In order to realize such stacked MOSFETs, channels such as III-V compound semiconductors and Ge are promising because they can be fabricated at low temperatures and are expected to have high mobility and injection speed. In our laboratory, we are investigating the realization of ultra-thin III-V-On-Insulator (III-V-OI) structures on Si substrates, and the performance improvement of III-V nMOSFETs using these structures aiming at application to 3D stacked CMOS. In addition, we are studying the device physics that determines their electrical characteristics. We have demonstrated the world's highest level of MOSFET performance using our original substrate formation technology using the smart cut method and other techniques, high-quality MOS interface control technology, and junction formation technology, which have attracted worldwide interest.

We are investigating the technology to realize ultra-thin Ge-On-Insulator (GOI) structures on Si substrates, the performance improvement of high-performance GOI CMOS using these structures, and the device physics that determines the electrical characteristics, with the aim of applying them to 3D integrated CMOS. We have demonstrated the world's highest mobility MOSFET performance under ultra-thin channels by using our original substrate formation technology that combines the oxidation concentration method, wafer bonding method, smart cut method, etc. with emphasis on optimal wafer orientation, channel strain control and high-quality MOS interface formation, which are extremely important for mobility improvement. We are also working on the demonstration of 3D CMOS combined with III-V-OI MOSFETs and the elucidation of the physical properties that determine the MOS interface and carrier transport characteristics, in order to establish the device physics.

In quantum computing systems, in addition to devices that manipulate qubits, CMOS integrated circuits that control signals are also indispensable. To scaling up the quantum computing system, it is necessary to place Si CMOS circuits that can operate at cryogenic temperatures such as 4K near the devices for qubit operation. For this purpose, it is mandatory to quantitatively clarify the behavior of MOS transistors at cryogenic temperatures with deep understanding of their physical mechanism. In our laboratory, we are conducting experimental and theoretical studies to clarify the electrical characteristics and reliability of Si MOSFETs at cryogenic temperatures and to quantify the physical parameters.