Embedded Files
Prepared by Yin Sun
Create Layout From Synthesized VHDL File
1: Log on to school server.
2: Go to the /tmp folder. Make a work directory for this lab under /tmp folder called “yourfoldername” Do not do this lab on the SDRIVE!!!!, Do this under the directory /tmp/yourfoldername
3: Copy related technology files:
a) download “snps_design_flow_tutorial.tar.gz” from https://drive.google.com/file/d/1_gFQNl1PWI86WcGOYl7mOhYDZnXrNgTI/view?usp=sharing to your SDRIVE using your web browser on the Windows machine.
b) copy this file to the directory “/tmp/yourfoldername “
c) On the Linux machine, untar the file using the command
tar –zxvf snps_design_flow_tutorial.tar.gz Do not do this in the SDRIVE!!!!
d) Go to the unzipped folder “snps_design_flow_tutorial”
e) Copy the directory “lab03_ic_compiler” to your /tmp/yourfoldername directory using the command:
Use this command : cp –r lab03_ic_compiler /tmp/yourfoldername
4: Start the Synopsys IC Compiler graphical user interface (GUI) from your work directory, /tmp/yourfoldername. To start the IC Compiler command-line interface, enter the following command at the UNIX or Linux prompt:
icc_shell -64bit –gui
5: This opens the IC Compiler top-level GUI window:
6: Setup libraries required for this lab. Open the File> Setup > Application Setup menu
7: Setup your Target library and Link library as follows. Click OK.
In IC Compiler, specify the .db files(library files) to use for your design by setting the target_library, and link_library variables.
The target_library variable specifies the .db library files containing the logic cells that can be used for optimization, for example, different NAND gates having various areas, drive strengths, delays, and power usage.
The link_library variable specifies the .db libraries containing all the logic cells that can be used to resolve hierarchical references in the design during execution of the link command.
8: Create the reference Milkyway library. To create the Milkyway design library, choose File > Create Library. The Create Library dialog box appears.
The create Library dialog box has options to specify the name of the new Milkyway library, the name of the associated technology file, the names of the associated Milkyway reference libraries, and the bus naming style. Enter yourfilename.mw into the “New library” box. Select the input reference libraries and the technology file. The input reference libraries is a folder. Select the folder itself, not its subfolder.
9: Set TLU+ files
TLUPlus is a binary table format that stores the RC coefficients for the timing simulations. The TLUPlus models enable accurate RC extraction by including the effects of width, space, density, and temperature on the resistance coefficients. Choose File > Set TLU+. Browse to the directories shown and select.
10: Import Design
Read the Verilog or VHDL file for the design by choosing File > Import Designs and specifying the files containing the Verilog design file. This design may contain a gate-level design in one or more files. For now, pick the Verilog file shown below – a simple Johnson [BDG1] counter. This particular file has already been synthesized to an RTL level design, containing specific connections between specific gates. A high level design containing something like “A<=B+C” would normally be synthesized to an RTL level design containing the specific gates required to perform the addition and store the results.
Setup is completed.
Please open the sdc file to understand the function of each line.
The previous steps were required to get your design into Synopsys and ready for layout. In the next parts of the lab you will perform the following:
a) Initialize floorplan,
b) Create rectangular power rings
c) Create power straps and preroute [BDG4] standard cells
d) Placement of standard cells
e) CTS (Clock Tree Synthesis)
f) Routing
g) DRC, LVS, and export GDSII [BDG5] file.
11: Initialize floorplan
Floorplan information includes the core area, top-level ports, and placement sites. To floorplan the design, choose Floorplan>Create Floorplan
You’ll next specify the control parameters and will indicate the method which specifies the size of the core area:
1. Aspect ratio – A ratio of height divided by width (the default)
2. Width & height – The exact width and height
3. Row number – A number of rows
4. Boundary – A fixed size according to the boundary defined in design planning
Example parameters are given below.
After you click OK, the following figure should appear:
12: Add power and ground rings
Select Preroute > Derive PG Connection. Fill out the table that comes up as shown below.
VDD VSS must be in capital letters!!!
To add power and ground rings, choose Preroute > Create Rings, select Rectangular Tab. The table below shows how to create two rings for VDD and VSS in metal 1 and 2 of the given widths and offsets.
After hitting OK, you should see something like:
13: Create power straps
Power straps are power connections that go between the power rings, and ensure a good connection everywhere within the design. After creating rectangular rings, the straps are automatically connected to the closest power and ground ring at, or beyond, both ends of the straps.
The create_power_straps command creates power straps in a design. Use a few wide straps rather than many thin straps to improve the placement quality and decrease the placement runtime.
The same as from Menu bar choose Preroute > Create Power Straps, and fill out the table as shown below.
After hitting OK:
14: Place the standard cells within the defined core area.
To run placement, choose Placement > Core Placement and Optimization. Fill out the table as shown.
You should get something like the following:
15: Clock tree synthesis
During clock tree synthesis, IC Compiler builds clock trees that meet the clock tree design rule constraints while balancing the loads and minimizing the clock skew. IC Compiler fixes the placement of the clock sinks, performs incremental logic and placement optimization, and fixes the placement of both the buffers and registers on the clock tree.
To perform clock tree synthesis and optimization, choose CTS > Core CTS and Optimization in the GUI. An example of filling out the table is shown below.
16: Pre-route standard cells
Connect power and ground pins in standard cells to the straps and rings and connect power and ground rails in the standard cells. To make sure the global router can recognize routing obstructions, Preroute the standard cells before performing global routing.
The same as from Menu bar choose Preroute > Preroute Standard Cells. Fill out the menu as shown.
The result is:
17: Route connections between the standard cells.
Finally, to route the design choose Route >Core Routing and Optimization. The core routing and optimization dialog box appears. Fill it out as follows.
The result:
18: Fill empty spaces.
insert_stdcell_filler this command fills empty spaces in standard cell rows with instances of master filler cells in the library. A common component or fill cells is decoupling capacitors, connected between VDD and VSS.
Type the command insert_stdcell_filler in the icc_shell control panel. For now, we will use the default filler cell, though the user could define which cells are used.
19: Design rule check
To do the design rule check, the Physical Signoff Options should be set first. To do this go to Verificaion> Set Physical Signoff Options menu. The setup window will open . It should be set up with the tool name, runset and map file as shown below. To perform a DRC choose [BDG6] Verification > Signoff DRC. (Something wrong with DRC executable icv)
20: LVS check
For check LVS errors choose Verification > LVS. The figure below shows an example of filling out the menu that pops up.
21: Export Stream (GDSII)
To write the data in specified library to a file in GDS format choose File > Export > Write Stream
Save it on your SDRIVE
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