Embedded Files
19Prepared by:
Hui Geng
Updated by Travis Schulze
Updated by Yin Sun
Updated by Muqi Ouyang
Data preparation
Ø Create a folder named CBIC_TEST under your SDRIVE home directory.
Ø Download the package syn.zip from the bottom of this page and store it in your CBIC_TEST folder.
Ø Extract the file
Note: The following files are necessary for a successful run of Encounter verify that all of these files are present after extraction, please copy your source file which passed simulation in Part 1 of this lab into ./source folder.
o Technology file: vtvt_tsmc250.lib
o Prepare Script file and constrain script
o Verilog netlist: counter.v
Login to the Linux System in EECH 107.
Open a terminal window.
Alternately, if you are logging in from a Windows system,
Click on the Start>XLaunch
Then, open Putty (Start> Programs > Putty ) and enter a remote login rcXXxece107.managed.mst.edu where XX can be any number from 36 to 40
Navigating back to the main screen on Putty select Open to connect
Ø In the command prompt, type the following commands to navigate to the new syn folder that you just extracted
o cd ~SDRIVE/CBIC_TEST/syn/
Prepare Scripts
Before you go through this tutorial, please go through the following script file to make sure you understand each sentence.
There are two script files, program run script file: rtl.tcl and timing constrain file: timing.sdc.
Copy "rtl.tcl" and "timing.sdc" to "syn" folder.
In order to open the script files, type the following commands in the terminal under ~/CBIC_TEST/syn
Ø "vim rtl.tcl"
Ø Then the following windows will be opened, you will need to update the file directories to match your own.
Ø Also you need put the file listed in corresponding folders ("vtvt_tsmc250.lib", "counter.v","timing.sdc").
Ø use "insert" to start editing; use "Esc" to stop editing; use ":wq" to save and quit vim.
Ø " vim timing.sdc &" to open the timing constraint file. Nothing needs to be changed in this file, but study it so you understand what it is doing.
To Start RC:
Ø Under syn folder, type “rc –gui” to start the software
NOTE: Do not use “rc -gui &”
NOTE on March 2022:
There may be errors on loading fonts during initialization of the GUI after execute "rc -gui", especially when you're using a Windows machine on your side. The reason is that the RTL Compiler GUI is looking for some fonts which are not included in Windows.
To solve this issue, please try to access the Linux servers in ECE107 from a Linux machine on your side. If you don't have your own Linux machine, there are 8 public Linux servers on campus in Computer Science building 213.
On the Linux machine, you can access the Linux servers in ECE107 using the command in the Linux terminal window: ssh -X um-ad\\<userID>@rcAAxece107.managed.mst.edu (where AA = 36 ~ 40).
Import Design
In the terminal window, execute the command below to import the rtl.tcl file:
include /mnt/dfs/ouyangm/users/ouyangm/VLSI_class/ta_advVLSI/CBIC_TEST/syn/script/rtl.tcl
Remember to change the path of the rtl.tcl file to your own.
If the import is done successfully, the design can be found in the GUI:
Ø Right-click "counter" in Hierarchy, and choose "open in" --> "schematic viewer" to generate gate-level schematic.
Check Result
Ø Go to ./output and ./report folder to check your result,
o Check the netlist after synthesis, which should be named as counter_syn.v,
o Check the timing result, if the Timing Slack is positive it means your design has no timing variation (this is a good thing)
Proceed to Part 3
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