Manual Layout, DRC, Parasitic Extraction- Legacy

Manual Layout, DRC, Parasitic Extraction

In this tutorial we are going to create the layout for a CMOS inverter Schematic.

Since we are doing a layout, we have to worry about the design rules and technology. We are going to use the AMI 0.6u technology which uses λ = 0.3 micron.

Consider the inverter schematic as shown below. We see that for both the transistors, we have W = 1.5u (5 λ) and L= 0.6u (2 λ)

Layout with Λ Rules:

In the Library Manager, select the library you created and go to File > New > Cell view and fill in cmos_inv for Cell Name, layout for View Name.

Important: Make sure "open with Layout GXL" is selected and select the checkbox below it.

Two windows should pop-up, the Virtuoso layout window screen and the LSW which is used for choosing the layers to be used:

In the Layout editor window, go to Options >Display.

In the grid controls, specify minor spacing and major spacing as 0.15

The distance between two consecutive horizontal or vertical grid points is now 0.15u (λ/2). All the shapes can now be drawn in terms of λ.

Let’s start with the nmos.

1. We know that the nmos is 5λ wide which gives us one dimension of the active region. The other dimension can be obtained by adding together all the features that are needed and their minimum sizes according to the design rules: we need the gate (length 2λ), two contacts of active to metal1 (2λ each), two minimum distances between contact and poly (2λ each) and two minimum overlap of active over contact (1.5λ each). If we add all of these together we get a total of 13λ. This means that our active region for the nmos is 5λx13λ. Let's draw a rectangle 5λx13 λ of nactive. First click on nactive in the LSW window, then do Create >Shape >Rectangle. On top right, are the X and Y absolute coordinates and dX and dY relative coordinates, these are very useful for drawing precise dimensions.

Note: You could use ruler tool in menu Tools>Create Ruler to get the accurate size of your shape.

2. Now let's draw the gate. We'll draw another rectangle, 2λ wide, in the middle of the active region so that it overlaps the area by 2λ on each side. Click on poly in the LSW and then draw a rectangle 2λ x 9λ.

3. Now we need to add the two contacts, both 2λ on each side and 2λ from poly and 1.5λ from the outside. Click on cc in the LSW and then draw a rectangle 2λx2λ.Then copy the rectangle to the position of the other contact by doing Edit -> Copy.

Alternately, you can also draw poly by choosing Create > Shape > Path instead of drawing a rectangle.

4. Now draw the substrate area-pactive rectangle that is 5λ on each side adjacent to the nmos transistor, then copy a contact into the middle of this region.

5. Now we need to surround the active area with select rectangles, nselect for the transistor and pselect for the substrate contact. These areas need to be 2λ larger than the active.

6. We need to add metal 1 above the contacts. This needs to overlap the contacts by 1λ.

With this, the nmos is complete.

Design Rules Check (DRC):

It is a good practice to check for the design rules as you design the layout.

Go to Verify > DRC

Enter the following for the Rules File:

/usr/local/cadence/ncsu-cdk-1.6.0.beta/techfile/divaDRC.rul

Click OK.

This will run the DRC on the layout and display the summary in the main virtuoso dialog window. If the design satisfies all the λ-rules, it will show 0 errors.

7. We have to now draw the pmos. The pmos is drawn in the same fashion except that nactive becomes pactive and vice-versa and nselect becomes pselect and vice-versa. In the end, you should get something like this.

8. Next we need to draw the nwell for the pmos. Draw a rectangle that extends over the pmos active area by 6λ.

9. We now need to route our schematic. First let's route the output, click on metal 1 and then Create -> Path and draw a path from the drain of the pmos to the drain of the nmos (right side). The path is only 3λ wide so draw it aligned to the right most side. You have to double click to end the path. Now draw another horizontal path towards the right as shown.

10. Now let's connect the input. Draw a poly path between the two gates. Observe that the default width of the poly line is correct: 2λ. Now start another horizontal poly path going to the left.

11. Now go to create > instance and select m1_poly contact from the NCSU_Techlib_ami06 library. Insert it as shown in the figure. Draw metal1from this contact towards left.

12. The only items left now are the vdd and gnd connections, we are going to use Create -> Polygon for those.

Make sure that the distance to other metal 1 (e.g. drain) is >3λ.

Save and run another DRC and make sure you have no errors.

13. Create the input, output and supply pins: To be consistent with the inverter schematic, we use Vin and Vout for the input and output.

For vdd!:

Click on Display Terminal Name Options and select the options as shown:

Draw a square pin on metal1 as shown. Repeat the procedure for gnd!, IN and OUT pins.For IN and OUT pins, the I/O type will be Input and Output respectively.

This completes our layout. Go to Verify > DRC and make sure you have no design rules errors.