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MST_ECE_EDA
Homepage
Available Tools and Libraries
Cadence Tutorials
Cadence Symbol Creation- Legacy
Cadence Virtuoso Schematic- Legacy
CMOS Inverter Schematic-45nm
Extracted View Simulation-45nm
Layout Vs. Schematic and Post Layout Simulation- Legacy
Manual Layout and Extraction- 45nm
Manual Layout, DRC, Parasitic Extraction- Legacy
Place and Route using encounter
Schematic Symbol Creation- 45nm
Schematic Testbench and Simulation- 45nm
Synthesize your design - RTL compiler
Test bench and Simulation with Spectre-Legacy
FAQs & Do's and Don'ts
FAQs, Rise Time, Fall Time
How to Measue Power
INTRO to VLSI
Create non-periodic signals with vpwlf
Synopsys-IC Compiler--This page still under construction
CpE6230
Alternate Cadence Tutorials (Legacy NCSU Libraries)
AMI06 Technology Lab1- Pad Frames Part 1
cell based full custom design
contact
CPE 6230
45nm Lab 1- Pad Frames
AMI06 Technology Lab1 Part 2-How to connect to pads and then simulate
Part 4- Encounter Timing Analysis
Final Project Information
Full Custom Design
How to Measure Propagation Delay
Pre-simulation using nclaunch
Standard cell based design
Synopsys IC Compilier_Education
MST_ECE_EDA
How to Measure Propagation Delay
Please see the attached pdf file.
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