Check out the attached Word Doc for lots of useful info to help you with the Final Project!
Sharing Files-
To share your work with your teammates you all need to be using same LIBRARY name. So I suggest when you start working that you all agree on a library name, ex. CPE5210_project.
Then you must close out Cadence before you copy or email the design files to your teammates. If you try to do it while Cadence is running the files will be locked when your teammate loads them.
GPDK Hints- Soft Errors
When we created the inverter layout we placed PMOS and Vdd! pin inside an NWELL.
When you place multiple gates in the same layout, you must place all these PMOS and Vdd! pins in the SAME NWELL. So just extend the NWELL's so they all touch and overlap.
If you don't you will get soft errors telling you that you have muliple taps.
Creating an input bit stream
If you want to create a specific input bit steam, for example "11001001", you can use the Vbit voltage source found in Analog Library.
Simply place an instance of Vbit, then in the properties you can define the bit stream you want. Remember to define voltage of bit 1 and bit 0 and to assign a reasonable rise and fall time, such as 50-100fs.