Embedded Files
Prepared by: Hui Geng
Updated by Travis Schulze
Updated by Yin Sun
Data preparation
Ø Create a folder named CBIC_TEST under your SDRIVE home directory.
Ø Download the package pr.zip from the bottom of this page and store it in your CBIC_TEST folder.
Ø Extract the file ("tar -zxvf XXXX.gz" or other command)
Note: The following files are necessary for a successful run of Encounter, so after your extraction, please copy your source file from Part 2 of this lab from RTL complier into the source folder
o Technology file: vtvt_tsmc250.lib
o LEF file of the library: vtvt_tsmc250.lef
o GDS2 Map file: vtvt_SoCE2df2.map
o Designers’ source file after synthesizing, Verilog netlist: counter_syn.v
To Start Cadence:
Login to the Linux System in EECH 107.
Open a terminal window.
Alternately, if you are logging in from a Windows system,
Click on the Start>XLaunch
Then, open Putty (Start> Programs > Putty ) and enter a remote login rcXXxece107.managed.mst.edu where XX can be any number from 36 to 40
On the Putty left hand menu, navigate to Connections -> SSH -> X11 and select enable X11 forwarding.
Navigating back to the main screen on Putty select Open to connect
Ø In the command prompt, type the following command to go to pr folder:
o cd ~SDRIVE/CBIC_TEST/pr/
Ø Under pr folder, type encounter to start the software
NOTE: Do not use “encounter &”
Import design
Ø Within the GUI, go to File->Import Design, Fill out the Basic and Advanced tabs as below:
Basic Tab:
o Verilog: counter_syn.v.
The verilog file from the synthesized design.
o Top Cell: counter
This should match the name of the main module from the verilog design, counter.v
o LEF Files: vtvt_tsmc250.lef
o Power Nets: vdd
o Ground Nets: vss
Leave all other fields as default.
Click OK. You may also save the configuration for future purposes.
After this, you will get: You may have to zoom our or zoom fit
Floor plan the design
Ø Go to Floorplan->Specify Floorplan.
Ø Specifying the Floorplan depends on the size of the design. You may follow the following settings or chose your own values.
Ø Fill out the form as shown below:
o Design Dimensions:
§ Size by Die->Size by: Aspect Ratio
§ Ratio (H/W): 1
§ Core utilization: 0.75
§ Core Margins by -> Core to IO Boundary
§ Core to Left: 50
§ Core to Top: 50
§ Core to Right: 50
§ Core to Bottom: 50
o Then click on OK
Ø After Floorplan
Add Power ring
Ø Go to Power->Power Planning->Add Rings.
Ø Fill out only the Basic tab.
o Add vdd and vss to the nets.
o Ring Configuration:
§ Change top/bottom layer to Metal5 H, and left/right layer to Metal4 V
§ Set Width as 15, spacing as 10, offset as 5
Ø After Add Rings
Add power Stripes
Ø Go to Power->Power Planning->Add Stripes and fill out the form as below.
Ø Set Configuration:
o Net(s) : add vdd and vss in
o Layer: Metal4
o Direction: Vertical
o Width: 3
o Spacing: 2
o Leave all other fields as default.
Ø Set Pattern:
o Set-to-set distance 30
Ø Select Apply.
Ø Set Configuration:
o Layer: Metal5
o Direction: Horizontal
o Leave all other fields as default.
Ø Select OK.
Ø 6After Adding Stripes
Route
Ø Go to Route->Special Route (SRoute).
o Net(s) : vdd vss
o For others: Use the default settings of the form.
Ø Select OK.
Ø After SRoute
Place Standard cells
Ø Go to Place->Standard Cell…
Use the default settings of the form
Make sure the View option is set to Physical view and not Floorplan view.
Ø After Placing Cells
Route the Design
Ø Go to Route -> NanoRoute -> Route
Ø Concurrent Routing Features
o Select the Timing Driven Option.
o Leave everything else as default. Select OK. This step may take some time, based on the size of your design.
Ø After Routing Nanoroute
12Add fill cells and metal fill
Ø PLACE->Physical Cell -> Add Filler...
Add filler cells in the design to allow all the wells to be at the same potential.
Ø Adding Filler cells
Verify final layout
Ø Go to Verify-> Verify Connectivity: You may keep the default settings.
The design should pass connectivity.
Ø Go to Verify -> Verify Geometry. Verify geometry with the default settings.
The design should pass this test as well.
Export GDS...
Ø Go to File->Save->GDS/OASIS
Fill out the form as below:
Output File: navigate to your CBIC_TEST/pr/output folder and type in a new file name which is
the name of the GDS file you wish to save. In my example "counter"
Map File: lib/vtvt_SocE2df2.map
This map file is used to map layer from SOC Encounter into df2.
Save and Exit
You have completed this tutorial. Save the design by going to File->Save Design.
Page updated
Report abuse