FAQs for lab1 and 2

Contents

FAQs for lab2. 1

1. Why I cannot find my design or I cannot edit my design, I saved it when I logout last time.

2. How to set input slew.

3. How to measure rise time.

4. How to measure the Tphl

5. How to export the schematic and layoutinto your report.

6. How to export the simulation waveform..

7. LVS Error 1:

8. How to extract DRC and LVS report.

1. Why I cannot find my design or I cannot edit my design, I saved it when I logout last time.

Please create your library in the following window, some of you lost you design when creating the library in library manager window (I think there may be some bugs in library manager window).

2. How to set input slew.

You will need to replace your DC source with a Vpulse source to make these changes.

3. How to measure rise time

Run your simulation using a pulse wave input and then use the tran analysis instead of DC in the Analog Design Environment.

First Open the Waveform Calculator from the waveform Plot, It looks like a little calculator

Fill out the form as shown. riseTime is found under Special Functions in the Function Panel.

When Ready click on the small table icon as shown by the mouse cursor in the image.

Falltime is similar.

4. How to measure the Tphl

Pay special attention to the net names make sure they match your waveform.

This configuration is for High to Low, input is rising output is falling.

5. How to export the schematic and layout into your report

Please refer the setting in the following figure, and I export my schematic as sch.png under /nethome/users/hgrfd/311_lab/results/

6. How to export the simulation waveform

7. LVS Error 1:

When I run LVS, it fails and I get the following error in the output log: *Error* Could not determine the node name for terminal 'progn(bn)'.... What's going on?

What we use in a schematic is the three-terminal MOS symbols ([np]mos from NCSU_Analog_Parts). By default, the three terminal MOS devices have their bulk nodes connected to "vdd!" (pmos) or "gnd!" (nmos), so you need to connect the body of PMOS to vdd and body of nmos to vss in your layout to pass LVS.

8.How to extract DRC and LVS report

For DRC you can use PrtScn(in the keyboard) or snipping tool to get the DRC result window.

For LVS, there are two ways to show your LVS result (Way 2 is better).

1. You can use the same way as DRC to get the window like following figure shows,

2. Or you can output the log file by clicking on output in LVS window as the following figure shown, then si.out window will appear, you can save this file as your LVS result report. (In fact, this file is located in your home folder/LVS/si.out if you do not change the run directory of LVS, you can just submit it as your LVS report.)