45nm Lab 1- Pad Frames

Prepared by:Travis Schulze

Before beginning this lab you must have the 45nm inverter schematic symbol and layout from the "Full Custom Design Tutorials".

Go back and complete those tutorial before beginning this lab.

In this lab you will layout a full pad frame for the 45nm technology.

These pads are found under the GIOLIB045 library. Take a moment to look through the available pad options.

You can use any pads you wish in your design but these are mandatory.

PADVDD- Power Pad

PADVSS- Ground Pad

PADVDDIOR- Power for the pad ring

PADVSSIOR- Ground for the pad ring

PADDI- input pad

PADDO- output pad

Write a script using the SKILL language that defines your pad frame

Ø Type gedit & in the terminal to open a new file, and write the script using SKILL language.

Here is an example of the script. (You can download this in the attachments at the bottom of this page)

We use this script to place the pads because it is critical that they line up exactly. It is very difficult to do this manually.

Ø The main function used in this code is dbCreateInst. The main parameters for this function you need are:

· “layout” indicates the view type.

· The following two parameters (list xpointv+no_pads*90 ypointv) are position coordinates (as shown in the following figure)

· The last one (R0 or R270) is the rotation angle.

Ø Save the text file in your home folder and name it as “***.il”.

Ø You could modify the code to create the pad frame you need, by specifying the type and the position of pad. You could also run and test your code directly from the Virtuoso log window.

Placing the Pads

Ø Create a new library to build your pad frame design. For example, I built pad_test, and created cell name test (cell type should be layout) as follows.

Ø Open the cellview window.

Ø Type load “xxx.il” in CIW of virtuoso, in which I named my script file as pad.il.

Ø Type placePadFrame(number) in CIW of virtuoso to indicate the number of pads in each side in your layout. Here I just place 4 pads in each side in my design, and you could use different numbers according to your design

Ø Then you will get the pads added in your design. Here I put two VDD pads, two GND pads, four input pads and four output pads in my design.

Ø Press shift+F to switch to the layout view of the pad frame, as in the following figure.

It is important to tie your inverter gnd! to the VSS pad and the VSSIOR pad.

Next you will place pins on all of the pads you used. Remember to use metal 1. Here I have filtered to show only Metal 1 for easier placement.

PADVSS and PADVSSIOR will both recieve gnd! pins

PADVDD will go to vdd!

PADVDDIOR will go to a different power source, I called mine vddior.

Run PVS DRC when your are done. You may see some errors related to the BONDPAD. This is ok.

Any other errors will need to be fixed before proceeding.

Create schematic view of the pad frame

Create a schematic view for your pad design.

You will place all of the same pads that are used in your layout and connect them up as shown.

NOTE- there are two corner pads in the library use the ones labeled "padIORINGCORNER". These will be toward the bottom of the list.

Place your inverter schematic symbol inside the pad frame and connect it as shown.

Note that there is no need to connect vdd and gnd to the inverter symbol. These have already been defined in the original schematic.

Add pins to Vin, Vout and vddior.

Closeup of the gnd! connections.

close up of the vdd! connection

Before you run LVS you must first alter one of the system files.

Download the file new.simrc from the bottom of this page.

It needs to be copied into your working directory (/gpdk) and renamed to just ".simrc"

You will need to delete the existing .simrc file.

Otherwise run LVS as before. Don't forget the additional Blackbox.pvl rule, it is included at the bottom of this page for easy reference. Results should match.

Run PVS QRC to get your av_extracted view for simulation.

Create a Schematic Symbol of the full pad frame schematic. Place it in a new testbench cellview.

Simulate to ensure proper function.

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Next add some Poly randomly to the inside of your padframe. The exact size and shape does not matter.

Now run a DRC check as before with your new rule ONLY. See form below.

Now here is the strange part, we actually WANT errors this time.

If you do not get any DRC errors, add more poly to your layout and run DRC again.

You should see something like this after DRC.

Next click on Open Errors.

Navigate to the file density.rdb. Remember you are running in YOUR /tmp/(username) directory.

You will need to select the "all files" option to see the *.rdb file. Open it.

Now you should see this. click on the Red Ball error line

DA is the total area inside your PadFrame

DA poly is the are of poly inside your PadFrame

and DV is the density of the poly as a percentage of total area.

As long as your poly density is between 15% and 50% then you are ok and you can stop.

Otherwise add or subtract poly until you are within that range.

Ø Generate a GDS file

MOSIS will only accept designs in CIF or GDS format.

Export procedure:

In the Virtuoso CIW window select File->export->stream, the below window should appear.

Fill it out as shown using your own file names. Hit Translate when ready to create the .gds file.

Once the translation process is complete and there are no errors, a GDS file will have been created in your home directory in the folder: /nethome/users/xxx