Embedded Files
Hui Geng
EECH 212
Connect PIN to pads
Ø Connect vdd/gnd pads
Because there are a lot of layers in the pads, it is difficult to connect the ports of inverter (inner circuit) to pads. We could just display one or several layers by setting available layers in LSW window. Taking the following layout as an example, select metal1 firstly, then click on NV located at the top of LSW, after pressing F6 in keyboard, the layout will just show the metal1 view. Similarly, if you also want to show metal2, just choose metal2, and then press F6. Next, we could connect vdd/gnd port of the inverter to vdd/gnd pad very easily, and the pad with red star is the vdd/gnd pad in following figure.
After zoom-in the detailed of the vdd/gnd pad as shown in the following figure, apparently, the port of inverter should be connected to the middle metal1 of vdd/gnd pad.
So the correct connection should be like:
If you want to show all layers of circuit again, just choose AV at the top of LSW, then press F6 in keyboard.
Ø Connect input or output pads
For padio, which is taken as input, after zoom-in the layout, we know it should be connected by Metal 2. If you are using Metal1 to connect the input port of inverter, you should connect it through m2_m1 vias as shown in the following figure.
For padout, which is taken as output, should also be connected by Metal 2, besides that you also should connect the upper small block to vdd, which is the enable pin of output pad.
Ø Label the pads
o After finishing all the connections, you should label the pads before extraction.
o Taking vdd pad as an example, we have connected the vdd of inverter to the vdd pad in the upper of pad rings (NOTE: you may have more than one vdd pads in your pad frame, but you can only label the one which you connected it to the vdd of your inverter)
Go to Create -> pins,
Terminal Names: vdd!
Select display Terminal Name
IO type: jumper for vdd! and gnd!, input for padio, and output for padout.
Then click on “Display Terminal Name Option” to open another window,
Height: 10
Layer: metal1(dg)
Click on OK for Display Terminal Name Option, and Create Pin window.
Draw rectangle on the pad as shown in the following figure.
Ø DRC and Extract the design
o In the layout window, execute the DRC and Extraction (following the tutorial: https://sites.google.com/a/mst.edu/eech106-eda/home/cadence-tutorials/layout).
o DRC result: you will get some DRC errors, if these errors are all about pads, please ignore them. However your extraction should be 0 error.
Ø Do tran simulation
o After you extract the design successfully, the next step is to create symbol of your layout design (following the tutorial: https://sites.google.com/a/mst.edu/eech106-eda/home/cadence-tutorials/cadence-symbol-creation). NOTE: The name of symbol must be the same as your layout.
Then please following the https://sites.google.com/a/mst.edu/eech106-eda/home/cadence-tutorials/test-bench-and-simulation-with-spectre
https://sites.google.com/a/mst.edu/eech106-eda/home/cadence-tutorials/layout-vs-schematic-and-post-layout-simulation to run simulation.
o NOTE
§ set the Setup-> Environment:
Add “extracted” before cmos_sch in Switch View list. All other setting should be the same as the pervious setting.
§ Do the tran simulation instead of dc. Change the settings according to the following figure shown.
Ø The correct result should be something like this:
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