Part 4- Encounter Timing Analysis

Prepared by: Travis Schulze

Now we can use Encounter to perform some simple timing analysis. We will use a slightly more complex design to make the analysis more meaningful.

Data preparation

Ø Download the two files from the bottom of this page and store them in your CBIC_TEST folder.

There is a VHDL design folder for a mini8051 processor and a new script file.

Place the VHDL files in your syn folder or alter the script to point to your folder of choice.

Ø In the command prompt, type the following commands to navigate to your syn folder

o cd ~SDRIVE/CBIC_TEST/syn/

Prepare Scripts

You will use the new mini8051_rtl.tcl script and the old timing.sdc file to synthesize the new design.

Edit the mini8051_rtl.tcl script to point to your directory.

After the design has synthesized review the timing and area reports. Make note of the timing slack and design area.

As an alternative you can pull up the timing information directly from the GUI. Go to Report/Timing/Worst Case

You will see the following screen. You will have to go to Options and check Show Schematic to see the schematic.

This Screen will show you the timing slack and the worst case path or Critical path. In the case of negative timing slack you will can see which gate or gates

are causing the problem and alter your design as needed.

Now open up the "timing.sdc" file found in the CBIC_TEST/script directory.

The first line defines the clock speed.

Change the clock period to speed up the clock. Save the file and re-synthesize your design.

What is the new timing slack? Based on this, calculate the fastest clock that still achieves timing closure.

Synthesize it and record your minimum timing slack achieved. Use this clock speed from now on.

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We are using the TSMC250 technology to synthesize this design. This is a 250nm technology.

When you open up the technology library you will see all of the parameters for the nominal operating condition.

All of the parameters can be altered. We will alter two of them and see how it affects the design.

Process is a number that represents the quality of the silicon. To alter it enter the following command in the command interface.

"set_attr process 1.4 [find /libraries -operating_condition _nominal_]"

Re-synthesize the design with command

"synthesize to_mapped"

What is the timing slack and area are now? Has the design routing changed?

Try changing the temperature, process and voltage to get the best area and slack.

You must change the attribute each time you synthesize. They revert back to nominal after each synthesis.

This can become a bit tedious. The technology library has several predefined operating conditions for you to use.

These are Best and Worst Case/ Commercial, Industrial and Military.

Use the command "set_attribute operating_conditions WCCOM /" to change to Worst Case Commercial.

Re-synthesize the design. Try all the operating conditions and see how they affect the design. Do any of them fail timing closure?