Layout Vs. Schematic and Post Layout Simulation- Legacy

Prepared by: Sambhav Kundaikar

Reviewed by Hui Geng

Layout Vs. Schematic

Ø Open the extracted layout of your design using Layout GXL.

Ø Go to Verify > LVS

Ø Select Form Contents in the window that pops up. Click on OK.

Ø The LVS window will now pop up. Select the library, cell and view for the schematic and the extracted views.

Ø Enter the following for the Rules file:

/usr/local/cadence/ncsu-cdk-1.6.0.beta/techfile/divaLVS.rul

Ø Click on Run and wait. A pop-up menu will then appear notifying you of the successful completion or failure of the LVS job. If successfully completed the job, you will see the following dialog box.

Ø Click on the Output button in the LVS window. You should see the following message:

Ø We see from the dialog box that there are no errors in the LVS comparison. However, there could have been errors if, for example, the W and L values of the transistors in the schematic window did not match with the W and L values of the transistors in the layout. If there are any errors, click on Error Display in the LVS menu to view what went wrong. The si.log will explain to you all the errors that it detected in both the schematic and layout views during the LVS comparison.

Post Layout Simulation

Ø The parasitic capacitances extracted according to how your layout is designed might be critical in affecting the actual performance of your design. In order to get an idea of how the design would work from your layout, you should perform a post-layout simulation from the extracted view. The procedure is identical to that for simulating from the schematic view.

Ø Open up the test bench for the inverter that you created in order to simulate the schematic.

Ø Go to Launch > ADE L. The Spectre window should appear.

Ø Go to Setup > Simulator/Directory/Host. A pop up window appears like below. Select Spectre as simulator, Click OK.

Ø Click Setup > Model Libraries and add the model files for nmos and pmos.

/usr/local/cadence/ncsu-cdk-1.6.0.beta/models/spectre/standalone/ami06N.m

/usr/local/cadence/ncsu-cdk-1.6.0.beta/models/spectre/standalone/ami06P.m

Ø Click on Setup -> Environment and you will see the Environment Options window open up. Originally, the Switch View List should contain the following items:

spectre cmos_sch cmos.sch schematic veriloga

Ø In order for Cadence to simulate through the extracted view of the layout design instead of the schematic view, you will include an additional item extracted in the Switch View List such that it now contains the following:

spectre cmos_sch cmos.sch extracted schematic veriloga ahdl

Note: Please make sure that you add “extracted” in front of schematic, then the simulation will be for extracted layout.

Ø Click OK.

Ø You can now perform the simulation in the same manner as described before in the tutorial for Spectre Simulations. The additional step allow you to take into account all the parasitic capacitances (eg. from interconnects and source/drain areas) that were contained in the extracted view of your layout. You may be able to notice subtle differences in the post-layout simulation results or waveforms as compared to the pre-layout schematic view results.