Synopsys-IC Compiler--This page still under construction

Prepared by Travis Schulze and Prateek, Updated by Yin Sun

You will need the following files and folders for this basic step.

These files are found in the .zip file found at the bottom of THIS PAGE!

Preliminary Steps-

Normally The fist step is to create a verilog netlist and sdc contrainst file using Cadence Encounter RTL Compiler.

Using the VHDL code that describes the design to generate the netlist and .sdc file according to the Cadence Standard Cell based tutorials.

You would then need to add the pad description to the netlist and edit the .sdc file.

However, this has already been done for you and the netlist and .sdc files are found in the .zip file on this page.

Begin Synopsys Place and Route-

Create a directory for your synopsys design, example; synopsys.

This must be created outside of the SDRIVE. This is the opposite of the Cadence tutorials which require you to work inside the SDRIVE.

Extract all of the files in the .zip to the synopsys directory.

Navigate to the synopsys directory

Ø Open the IC compiler GUI using the following in the command prompt

icc_shell -64bit -gui

Ø Set the target library by typing in the following command in the icc gui shell. The first library contains all of the standard cells. The second contains the I/O pads.

set_app_var target_library "m35sm330s_typ.db cb35io122d_typ.db"

set_app_var target_library "m35sm330s_max.db cb35io122d_typ.db"

This is the ICC GUI window

Ø Link in the target by using the following command

set_app_var link_library "* $target_library"

Ø Then enter the following two commands

set mw_logic0_net vss

set mw_logic1_net vdd

Ø Now go to FILE> Create Library

Add the following files and folders to the window using your file and directory paths

In the "Technology file" space use the Astro_HL35SM14_130412.tf found in the HL35S3350M1X_9track_astroteck_130415/4LM/STD folder

In the "Input Reference Libraries" add the m35sm330s_4lm folder

Found in m35sm330s_HL35s_astrofram_130412/STD/

cb35io122d_4lm

Found in Astro_DK_cb35io122_fram_080306/

use the whole folder do not open the folder.

Check in the "Open library" check box and press OK

Ø Now Go to FILE>SET TLU+

Fill in the window as shown, again using your own file path

HL35S3350M1X_9track_astroteck_130415/4LM/STD

The mapping file is found

HL35S3350M1X_9track_astroteck_130415/4LM/

Press OK

Ø In the icc gui command type in

check_tlu_plus_files

Ø Ensure that in the files show “passed ” in the command window

Ø Now go to FILE> Import> Read Verilog

Choose the verilog netlist 8051_chip.v.

Press OK

Ø Successful reading of the netlist file will open up a layout window. This may take a while.

Troubleshooting READ Verilog step

The read Verilog step may fail on the first attempt.

If you see this error, Close IC_Compiler. Then re-open it and Open the library you created.

You will also need to re-link the libraries just as you did before and re-input the TLU+ files.

Then try to read in the Verilog file again.

Ø Now in the IC Compiler main window, Go to FILE> Import > Read SDC

Choose the .sdc file 8051_chip.sdc.

Ø Choose the .sdc file, and change the version to match your file. It should be 1.7 but make sure. Press OK

Ø Successful reading of the sdc file should show a “1” in the command window

Ø Now we will set up the pad ring. This file tells Synopsys to create power, ground and corner pads with a script file.

Take a moment to read this file.

From the ICC shell go to FILE>Execute Script

Input the "create_phy_Cell.tcl" file

Ø Now we will create the rest of the pads and tell Synopsys where we want them placed with another script file.

Take some time to read and understand this file.

From the Layout Window select Floorplan> read_pin_pad_physical_constraints

Select the 8051_io.tdf file, Press OK

Ø Now in the IC Compiler Layout Window Go to, FLOORPLAN> Create Floorplan

Fill in the options as shown below. We will do this twice. The first time we will check the Pad Limit box. then click Apply.

Then unclick the Pad Limit box and click OK. By doing this twice we will create a minimum size design limited by the number of pads.

Ø A floorplan should appear with the standard cells besides it as shown in the figure below

To confirm the pads are lined up properly without any spaces inbetween enter the following command into the ICC Shell

There should not be any filler added.

insert_pad_filler -cell "iofiller"

Ø Now in the IC Compiler layout window go to, PREROUTE> Derive PG Connections

Ø Check in the Manual Connection option and fill the details as shown below , then press OK

Ø In the IC Compiler Layout Window go to, PREROUTE> Create Rings

Ø Select the Rectangular option

Ø Type in vdd vss in the Nets option and fill in the rest as shown below and click OK

Ø The power ground rings should appear in the layout

ØFrom the layout window select PREROUTE> Preroute Instances, accept the defaults and click OK.

The power and ground rings should now be connected the the VDD and VSS pads as shown below. Confirm this.

Ø In the IC Compiler layout window go to, PREROUTE> Preroute Standard Cells

Ø Go to the Routing Options and check in the boxes as shown below and click OK

Ø Now in the IC Compiler main window , type in

create_fp_placement in the icc_shell command prompt

Ø All the standard cells should get placed in the floorplan as shown in the figure below

Ø Now type in

legalize_fp_placement in the icc_shell command prompt

It should show “1” in the command window

Ø Now type in

place_opt in the icc_shell command prompt

Ø Again It should show “1” in the command window for successful execution

Ø Now type in

set_fix_hold [all_clocks ] in the icc_shell command prompt

Ø Now type in

clock_opt in the icc_shell command prompt

Ø You should see the clock tree synthesis routing in the layout as below

Ø Now type in

route_opt in the icc_shell command prompt

Ø You should now get a routed layout in the layout window as shown below.

We must now confirm that the layout and netlist match. Go to Verification>LVS. Accept the defaults and click OK.

An error window will appear. Most likely it will have erros the first time. Click on the errors to see what each means.

If you have a short between VDD and VSS, re-run the Derive PG connections step.

If you still have further errors you will need to re-run the placement and routing steps.

Pre-route Instances

Pre-route Standard Cells

Route

If you still have errors run them all again.

When LVS generates zero errors then you can proceed.

The next step is to fill in the extra space in the layout with a standard cell.

In the layout window, select Finishing- Insert Standard Cell Filler

Fill out the window as shown.

The layout is now completely full.

Ø Now in the ICC Shell we will set up the GDS file export.

Input the following command

set_write_stream_options -map_layer HL35S.layerMap -child_depth 20 -flatten_via

Again check for successful execution shown by '1' in the window

Then go to

FILE> Export> Write Stream

Ø Check in the GDSII option and write the name with which you want to save the file in the Stream file name to write option and click OK

Ø The command window should show the following message for successful write

Ø Save the design before exiting.