Manual Layout and Extraction- 45nm

Prepared by Travis Schulze; Updated by Yin Sun

Updated by Muqi Ouyang, March 2022

In this tutorial we are going to create the layout for our CMOS inverter Schematic.

Since we are doing a layout, we have to worry about the design rules and technology. The Design rules for the GPDK 45nm library are found under the Cadence Guides page of this site.

Layout with Pcells

In the Library Manager, select the library you created and go to File > New > Cell view and fill in cmos_inv for Cell Name, layout for View Name. It is important again that the cell name match the schematic cell name and that only the cell Type changes.

Important: Make sure "open with Layout L" is selected and select the checkbox below it.

The Virtuoso layout editing window screen will appear. Notice all the different layer options on the left.

In the Layout editor window, go to Options >Display.

In the grid controls, specify minor spacing to .05, major spacing .05 and both x and y snap to .005. And check Pin Names.

Note: this is not currently saving properly. You may have to do this each time you open the layout.

Let’s start with the NMOS. The transistors can be placed a complete units called Pcells. Go to Create>Instance, in the create instance box select Browse. This will open the Library browser. Navigate as shown below and select the layout view of the nmos1v.

Place the NMOS. It will show up as a red box.

Hit Shift+F to change views.

Now you can see all the layers that make up the NMOS. Take a minute to explore all the layers that are used. To the left select Layers> Used checkbox. This will filter the layer list to only those layers currently in use. When you are done uncheck the box.

Now we will place the PMOS just as we did the NMOS. Place it above the NMOS.

Next we will start to connect the transistors. select Creat>wireing>wire (shortcut p).

After Placing the wire you can change the width by Right Clicking on it and setting the width to 0.06.

Select Metal1 as the layer for the vdd, gnd and output but connect the gates with poly. The layers are selected by highlighting that layer in layer menu on the left of the screen. Use the following diargram as a guide.

You will notice there are some additional elements in this layout. These are vias. The top and bottom vias are to gnd and vdd the left most via will allow us to connect our gate poly to the metal1 layer for proper connections.

To add vias go to Create> Via. In the Via Definition Drop Down, select M1_PO for M1 to Poly and set rows and columns to 2. Set the Net Name to Vin. This can be done by right click the Via and edit through properties. Add the Route Net Name under connectivity tab. Place this via as shown in the diagram.

Then create a new via type M1_NWELL and change the net name to vdd!. It should also have 2 rows and 2 columns. Place it above the PMOS.

Create one more for gnd! using M1_PSUB and place it under the NMOS. Connect all the vias up as shown.

Now that we have added a Via that connects to the NWELL above the PMOS we need to connect the NWELL of the PMOS to the NWELL of the via. To do this go to Create>Shap>rectangle and select the NWELL layer.

Place the box so that the vdd via and the PMOS NWELL are both contained within. When you are done you will have something like this.

Finally we need to add pins to the layout. This is done exactly as before. Go to Create> Pin. and create pins for Vin, Vout, gnd! and vdd!.

Check the box for Create Label and click on Options. Set the label Height to .03. Set Layer Name to "Same as Pin". Set Layer Purpose to "label".

Important- When you place the label it must be completely inside the pin.

Make sure you select Metal1 as the layer (or to match what ever layer you want the pin in) and place them as shown in the diagram. The placement is slightly different from the Schematic view. These pins will be box shaped, so click once where you want to place the pin and then drag out to create the box. A third click will place the label.

Important- the label must be completely enclosed within the pin.

Select the appropriate I/O type for each pin, input, output or jumper for VDD and GND

The Layout is now done and we will now check it against the design rules using PVS DRC.

Note:

To run DRC and LVS using PVS, you have to start the CIW in a local directory, not your S-drive.

You can do this by:

1. Close the current working windows and CIW.

2. Go to the start folder by: cd ~

3. Make a directory: mkdir myFolderName

4. Go to the newly created folder and start the CIW there:

cd myFolderName

gpdk045.sh &

5. Include your library:

Tools --> Labrary Path Manager

Edit --> Add Library

Navigate to your previous working folder, and add the inverter library:

6. OK, and File --> Save in the previous window.

PVSDRC-

First we need to go to the top toolbar and under Launch, Plugins, click PVS. PVS will now appear in the toolbar. If the PVS already appears at the tool bar, you do not need this step.

Under PVS, click on Run DRC, you will see the first DRC window. Fill out the run directory just as shown only use your own username(ysc26 is my username). It must be in /tmp folder.

Then Click on Rules, you will see the second DRC window. In this window you will need to navigate to the rules file.

Click on the navigation button next to Technology Mapping File. Navigate to /opt/cadence/gpdk045_v_4_0/pvtech.lib.

After clicking on pvtech.lib use the dropdowns to fill out the rest of the form.

Take a minute to familiarize yourself with the other widnows, input, output etc. But we will not need them now.

Click on Apply to run DRC.

Hit OK. The DRC will Run. If you have errors you will see a popup like this one.

You can click on the errors and the lower window will explain them and the layout will zoom to the error so you can find it.

After you fix it re-run DRC as needed.

When you have zero errors you will see this.

Layout Versus Schematic Check- PVS LVS

Now that the Layout has passed the design rules we need to check it against the schematic using PVS LVS.

Click on LVS under the PVS toolbar option. Set up your directory as shown using your own username. /tmp/XXXXXX/LVS

Click on the Rules tab and fill out the page as shown. You will find the blackbox.pvl file at the bottom of this page. You must download it yourself.

To add the blackbox.pvl into the window, click the "..." button on the right of the LVS window.

Go to the input tab and verify that correct layout and schematic views are selected for comparison.

Finally click on Output, scroll to the bottom of the page and check the box next to Create QRC Data. (This is not required by the lab)

Hit apply when you are ready.

Results should match. If not use the LVS Debug Environment to troubleshoot.

Parasitic Extraction: (to be updated)

The last step before simulation is to extract the parasitic capacitances using PVS QRC.

Go to QRC, Run PVS-QRC. You will set the run directory as before /tmp/(username)/QRC.

When the QRC opens set up each tab as shown.

Hit Ok to run.

A new view will be created when complete called av_extracted. Open it.

Hit Shift+F to switch views and Ctl+F to switch back.

To view the internal connections go to Options> Display and select the Nets checkbox.

If you zoom in you can see the tiny Capacitors.

Save your work and your layout is done.