Publications

Conference

• 1. Power-efficient Range-match-based Packet Classification on FPGA

     1. • Full paper at International Conference on Field-programmable Logic and Applications (FPL '15), Yun R. Qu, Viktor Prasanna

  2. Large-scale Packet Classification on FPGA

     1. • Full paper at IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP '15), Shijie Zhou, Yun R. Qu, Viktor Prasanna

  3. Optimizing Many-field Packet Classification on FPGA, multi-core General Purpose Processor, and GPU

     1. • Full paper at ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '15), Yun R. Qu, Hao H. Zhang, Shijie Zhou, Vikor K. Prasanna

  4. Enabling High Throughput and Virtualization for Traffic Classification on FPGA

     1. • Full paper at IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '15), Yun R. Qu, Viktor Prasanna

  5. High-Throughput Hash-based Online Traffic Classification Engines on FPGA

     1. • Full paper at International Conference on Reconfigurable Computing and FPGAs (ReConfig '14), Vaibhav R. Gandhi, Yun R. Qu, Viktor Prasanna

  6. Compact Hash Tables for High-performance Traffic Classification on Multi-core Processors

     1. • Full paper at IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD '14), Yun R. Qu, Viktor Prasanna

  7. Scalable and Dynamically Updatable Lookup Engine for Decision-trees on FPGA

     1. • Full paper at IEEE High Performance Extreme Computing Conference (HPEC '14), Yun R. Qu, Viktor Prasanna

  8. Performance Modeling and Optimizations for Decomposition-based Large-scale Packet Classification on Multi-core Processors

     1. • Full paper at International Conference on High Performance Switching and Routing (HPSR '14), Yun R. Qu, Shijie Zhou, Viktor Prasanna

  9. High-Throughput Traffic Classification on Multi-core Processors

     1. • Full paper at International Conference on High Performance Switching and Routing (HPSR '14), Da Tong, Yun R. Qu, Viktor Prasanna

  10. Scalable Many-field Packet Classification on Multi-core Processors

      1. • Full paper at International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD '13), Yun R. Qu, Shijie Zhou, Viktor Prasanna

  11. High-performance Architecture for Dynamically Updatable Packet Classification on FPGA

      1. • Full paper at ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '13), Yun R. Qu, Shijie Zhou, Viktor Prasanna

  12. Multi-core Implementation of Decomposition-based Packet Classification Algorithms

      1. • Full paper at International Conference on Parallel Computing Techniques (PaCT '13), Shijie Zhou, Yun R. Qu, Viktor Prasanna

  13. Architecture and Performance Models for Scalable IP Lookup Engines on FPGA

      1. • Full paper at International Conference on High Performance Switching and Routing (HPSR '13), Yi-Hua E. Yang, Yun R. Qu, Swapnil Haria, Viktor Prasanna

  14. Fast Dynamically Updatable Packet Classifier on FPGA

      1. • Short paper at International Conference on Field Programmable Logic and Applications (FPL '13), Yun R. Qu, Viktor Prasanna

  15. High-performance Pipelined Architecture for Tree-based IP lookup Engine on FPGA

      1. • Full paper at Reconfigurable Architectures Workshop (RAW '13), Yun R. Qu, Viktor Prasanna

  16. Large-scale Multi-flow Regular Expression Matching on FPGA

      1. • Full paper at IEEE Conference on High Performance Switching and Routing (HPSR '12), Yun R. Qu, Yi-Hua Edward Yang, Viktor Prasanna

  17. Multi-stream Regular Expression Matching on FPGA

      1. • Full paper at International Conference on Reconfigurable Computing and FPGAs (ReConfig '11), Yun R. Qu, Yi-Hua Edward Yang, Viktor Prasanna

  18. A Distributed Cooperative Product Code for Multi-source Multi-relay Single-destination Wireless Network

      1. • Full paper at Asia-Pacific conference on Communications (APCC '09), Zhisheng Xia, Yun R. Qu, Hui Yu, Youyun Xu

Journals

• 1. Accelerating Decision Tree Based Traffic Classification on FPGA and Multicore Platforms

     1. • Journal paper at IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28, no. 1, pp. 3046-3059, Da Tong, Yun R. Qu, Viktor Prasanna

  2. Fast Online Set Intersection for Network Processing on FPGA

     1. • Journal paper at IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 1, pp. 3214-3225, Nov 2016, Yun R. Qu, Viktor Prasanna

  3. Compact Hash Tables for Decision-trees

     1. • Journal paper at Parallel Computing (PARCO), 2016, pp. 121-127, Yun R. Qu, Viktor Prasanna

  4. High-performance and Dynamically Updatable Packet Classification Engine on FPGA

     1. • Journal paper at IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 1, pp. 197-209, Jan 2016, Yun R. Qu, Viktor Prasanna

  5. A Decomposition-based Approach for Scalable Many-field Packet Classification on Multi-core Processors

     1. • Journal paper at International Journal of Parallel Programming (IJPP), pp. 1-23, Sep 2014, Yun R. Qu, Shijie Zhou, Viktor Prasanna

  6. Multi-core Implementation of Decomposition-based Packet Classification Algorithms

     1. • Journal paper at the Journal of Supercomputing, Volume 69, 2014, pp. 34-42, Shijie Zhou, Yun R. Qu, Viktor Prasanna

Book Chapters

• 1. Packet Classification on Multi-core Platforms

     1. • Handbook on Data Centers, by Khan, Samee Ullah, Zomaya, Albert Y. (Eds.) 2015, XIII, 1334 p.