Power-efficient Range-match-based Packet Classification on FPGA
Full paper at International Conference on Field-programmable Logic and Applications (FPL '15), Yun R. Qu, Viktor Prasanna
Large-scale Packet Classification on FPGA
Full paper at IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP '15), Shijie Zhou, Yun R. Qu, Viktor Prasanna
Optimizing Many-field Packet Classification on FPGA, multi-core General Purpose Processor, and GPU
Full paper at ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '15), Yun R. Qu, Hao H. Zhang, Shijie Zhou, Vikor K. Prasanna
Enabling High Throughput and Virtualization for Traffic Classification on FPGA
Full paper at IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM '15), Yun R. Qu, Viktor Prasanna
High-Throughput Hash-based Online Traffic Classification Engines on FPGA
Full paper at International Conference on Reconfigurable Computing and FPGAs (ReConfig '14), Vaibhav R. Gandhi, Yun R. Qu, Viktor Prasanna
Compact Hash Tables for High-performance Traffic Classification on Multi-core Processors
Full paper at IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD '14), Yun R. Qu, Viktor Prasanna
Scalable and Dynamically Updatable Lookup Engine for Decision-trees on FPGA
Full paper at IEEE High Performance Extreme Computing Conference (HPEC '14), Yun R. Qu, Viktor Prasanna
Performance Modeling and Optimizations for Decomposition-based Large-scale Packet Classification on Multi-core Processors
Full paper at International Conference on High Performance Switching and Routing (HPSR '14), Yun R. Qu, Shijie Zhou, Viktor Prasanna
High-Throughput Traffic Classification on Multi-core Processors
Full paper at International Conference on High Performance Switching and Routing (HPSR '14), Da Tong, Yun R. Qu, Viktor Prasanna
Scalable Many-field Packet Classification on Multi-core Processors
Full paper at International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD '13), Yun R. Qu, Shijie Zhou, Viktor Prasanna
High-performance Architecture for Dynamically Updatable Packet Classification on FPGA
Full paper at ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS '13), Yun R. Qu, Shijie Zhou, Viktor Prasanna
Multi-core Implementation of Decomposition-based Packet Classification Algorithms
Full paper at International Conference on Parallel Computing Techniques (PaCT '13), Shijie Zhou, Yun R. Qu, Viktor Prasanna
Architecture and Performance Models for Scalable IP Lookup Engines on FPGA
Full paper at International Conference on High Performance Switching and Routing (HPSR '13), Yi-Hua E. Yang, Yun R. Qu, Swapnil Haria, Viktor Prasanna
Fast Dynamically Updatable Packet Classifier on FPGA
Short paper at International Conference on Field Programmable Logic and Applications (FPL '13), Yun R. Qu, Viktor Prasanna
High-performance Pipelined Architecture for Tree-based IP lookup Engine on FPGA
Full paper at Reconfigurable Architectures Workshop (RAW '13), Yun R. Qu, Viktor Prasanna
Large-scale Multi-flow Regular Expression Matching on FPGA
Full paper at IEEE Conference on High Performance Switching and Routing (HPSR '12), Yun R. Qu, Yi-Hua Edward Yang, Viktor Prasanna
Multi-stream Regular Expression Matching on FPGA
Full paper at International Conference on Reconfigurable Computing and FPGAs (ReConfig '11), Yun R. Qu, Yi-Hua Edward Yang, Viktor Prasanna
A Distributed Cooperative Product Code for Multi-source Multi-relay Single-destination Wireless Network
Full paper at Asia-Pacific conference on Communications (APCC '09), Zhisheng Xia, Yun R. Qu, Hui Yu, Youyun Xu
Accelerating Decision Tree Based Traffic Classification on FPGA and Multicore Platforms
Journal paper at IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28, no. 1, pp. 3046-3059, Da Tong, Yun R. Qu, Viktor Prasanna
Fast Online Set Intersection for Network Processing on FPGA
Journal paper at IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 1, pp. 3214-3225, Nov 2016, Yun R. Qu, Viktor Prasanna
Compact Hash Tables for Decision-trees
Journal paper at Parallel Computing (PARCO), 2016, pp. 121-127, Yun R. Qu, Viktor Prasanna
High-performance and Dynamically Updatable Packet Classification Engine on FPGA
Journal paper at IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 1, pp. 197-209, Jan 2016, Yun R. Qu, Viktor Prasanna
A Decomposition-based Approach for Scalable Many-field Packet Classification on Multi-core Processors
Journal paper at International Journal of Parallel Programming (IJPP), pp. 1-23, Sep 2014, Yun R. Qu, Shijie Zhou, Viktor Prasanna
Multi-core Implementation of Decomposition-based Packet Classification Algorithms
Journal paper at the Journal of Supercomputing, Volume 69, 2014, pp. 34-42, Shijie Zhou, Yun R. Qu, Viktor Prasanna
Packet Classification on Multi-core Platforms
Handbook on Data Centers, by Khan, Samee Ullah, Zomaya, Albert Y. (Eds.) 2015, XIII, 1334 p.