September 27, 2015

Every RTL design engineer should know the techniques to cross clock domains. I will first introduce one in this article: the use of synchronizer. If I ask an engineer to draw the RTL block of a synchronizer, he should NEVER draw something like this:

In this figure, let us assume the output from the first clock domain (synchronized to "clk1") is generated by some combinational logic. In this case, the figure shown on the right side does not work. Why?

We know that combinational logic can have glitches. For example, an output "d" generated by the function d=a|(b&c) can have glitches before the output stabilizes. Even if we don't talk about noise or signal interference, we still can have glitches because the inputs (in this example, "a", "b", and "c") can arrive at the final gate at different time. If by any chance, the 2 concatenated registers capture the glitches, the outputs from the second clock domain, synchronized by "clk2", will be wrong!

Then what is the right way to do this?

The solution is very easy. We show the right way of using a synchronizer on the right side this time. The key is to use another register, synchronized by "clk1" to isolate the combination logic from the other two registers. This isolation prevents the glitches from the first clock domain getting into the second clock domain. So next time an interviewer asks you to draw a synchronizer, always draw 3 registers instead of 2!