Level Shifter

October 10, 2015


When we want to cross the design boundaries, the clock domain crossing is not the whole story. Sometimes you may want to cross power domains as well. For example, the CPU and the DRAM may require different voltages. It is also beneficial to separate power domains for power gating purposes. However, it remains a challenging problem for signals to pass through the power domain boundaries. In general, there are two cases:

  1. High-to-low: Passing a signal from a domain with a higher voltage to a domain with a lower voltage.

  2. Low-to-high: Passing a signal from a domain with a lower voltage to a domain with a higher voltage.

The first case is easy. An ordinary inverter working in a low-voltage domain in principle can take higher voltages as inputs. This will not be a problem if the two voltages differ slightly from each other. For example, if we want to transfer the signal from a 1.8V domain to a 1.5 domain, we can port the 1.8V signals out to the inverter in the 1.5V domain. The logic values of "0" and "1" are still valid inputs.


Complication arises when we want to do it in the other way around. If we want to pass a signal in a low-voltage domain into a high-voltage domain, it is very likely that the low-voltage signals trigger a large crossbar current on the receiving gate; for example, a 1.5V signal may cause both the PMOS and NMOS of the inverter in the 1.8V domain to work in the saturation region, leaking a significant amount of power and damaging the transistors. Hence, we need the so-called level shifter in this case.

The level shifter has an organization shown in the figure above. This organization should look familiar to most of the hardware designers. I will mention a few possible connections:

  • A: Vdd, B: via an NMOS (controlled by SENSE) to GND, C: OUT, D: OUT_bar, E: BL (Bit Line), F: BL_bar. This design is the sense amplifier of the SRAM.

  • A: Vdd_high, B: GND, C: OUT_bar, D: OUT, E: IN, F: IN_bar (inverted in Vdd_low domain). This design is the level shifter translating low-voltage signals IN to high-voltage signals OUT.

Remember that this design won't work if we connect A to GND, and B to Vdd. It is still important since in many designs we can disable this block by simply flipping the polarity of the power and ground.