November 17, 2017

I have been recently packaging IPs for my projects. The standard flow of doing this is shown below:

Step 1: Create a Vivado project with the following Verilog source file, as an example.

module video_xor(rgb0, rgb1, hsync1, vsync1, vde1, rgb2, hsync2, vsync2, vde2);

input [23:0] rgb0, rgb1;

input hsync1, vsync1, vde1;

output reg [23:0] rgb2;

output reg hsync2, vsync2, vde2;

always @ (*) begin

rgb2 <= rgb0 ^ rgb1;

hsync2 <= hsync1;

vsync2 <= vsync1;

vde2 <= vde1;

end

endmodule

Step 2: Synthesis the design to verify the hardware code.

Step 3: Create and package the IP.

Step 4: Adjust the settings.

If you do not adjust anything, and instead directly package it, you will see the block diagram as shown below.

This is bad because usually users always want to leverage the design automation provided by the tool; the raw interfaces shown in the above figure are not recognizable by the tool. The key is to set them as a known interface type.

Choose a known interface definition as below. The mode should be slave, since inputs are driven by other modules. For output pins, the mode should be master.

And map the ports one by one.

Step 5: Check the mapping, and package the IP.

And now the block diagram looks like the following.

Since those interfaces are now recognizable by the tool, you can package the IP and automatically connect them in a bigger design!