When the processor is reset, the hardware sets the Program Counter (PC) to 0x0000 and starts executing by fetching the instruction at 0x0000. At this location, we usually have an exception vector table which will be the system default. The exception vector table follows a regular pattern, and consists of undefined instruction, SWI, prefetch abort, data abort, not used, IRQ, FIQ, etc.
When the hardware takes an exception, the PC should automatically set to the address of the relevant exception vector and the processor begins executing instructions from that address. When the processor comes out of reset, the PC is automatically set to "base address + 0". An undefined instruction sets the PC to "base address + 4", and SWI sets the PC to "base address + 8", etc. The base address of the vector table can be either 0x00000000, 0xFFFF0000, or VBAR (user defined), depending on the processor and configuration. For example, we can change the exception vector table on ARM-v7 by using the assembly:
mcr p15, 0, <Rd>, c12, c0, 0
A full description of the above code can be found here. To be more specific, we have used the following assembly code in "FreeRTOS_asm_vectors.S":
ldr r0, =_freertos_vector_table
mcr p15, 0, r0, c12, c0, 0
The above piece of code is provided in a reference design on Zed-board. Note that the corresponding function should be called during run time to change the vector table from default to freertos_vector_table.