For RTL designers, there are several questions frequently asked during interviews. I am going to summarize them in this article.
Computer architecture: Direct-mapped cache, set-associative cache, and fully-associative cache. Virtual-physical address translation. Page fault.
Hardware coding: Verilog blocking / non-blocking statement. Delayed-assignement and delayed-evaluation.
Digital design basics: The use of MUX to construct any combination and sequential logic (including double-edge FF). Glitch-free clock multiplexer and other designs.
Crossing clock domain and STA: Ways to cross clock domains. Setup time, hold time, clock period, clock skew, metastability, etc.
The above concepts contribute most of the must-ask interview questions. Many interviewers tends to ask more challenging questions based on these basic concepts. For example, what are the options to fix the setup time violation?
Of course, some interviewers also give puzzles. I will use another article to cover them later.