No one in our group is still using Xilinx ISE design suite after the Vivado design suite is available. However, to keep a record, let's see how scripting works in Xilinx ISE. Such a technique can improve design time significantly, since no GUI has to be inferred.
Before start, besides the design files (*.v or/and *.vhd), you will need 3 more files. The following files are just giving an example; the naming convention does not have to be followed. In this example, suppose we are using Virtex XC6VLX760 ff1760 -2 FPGA.
"test_xc6vlx760-ff1760-2.prj". This file contains all the design files:
verilog work bram_dp_256.v
verilog work distRAM_sp.v
verilog work pipe_reg.v
verilog work pipeline.v
verilog work qstage.v
"test_xc6vlx760-ff1760-2.xst". This file configures the compilation:
set -tmpdir "./xstcmdl/tmpdir"
set -xsthdpdir "./xstcmdl"
run
-ifn test_xc6vlx760-ff1760-2.prj
-ofn test_xc6vlx760-ff1760-2.ngc
-top pipeline
-p xc6vlx760-ff1760-2
-ifmt mixed
-ofmt ngc
-opt_mode speed
-glob_opt allclocknets
-read_cores no
-fsm_extract no
#-register_balancing no
#-register_duplication yes
#-slice_packing yes
-iob auto
-equivalent_register_removal no
"test_xc6vlx760-ff1760-2.sh". This file contains the program commands:
#!/bin/sh
rm -f finished_*.mark
. /opt/Xilinx/14.5/ISE_DS/settings64.sh
export XILINXD_LICENSE_FILE=2100@kalu.usc.edu
xst -intstyle silent -ifn test_xc6vlx760-ff1760-2.xst ; sleep 10
ngdbuild -intstyle silent test_xc6vlx760-ff1760-2.ngc test_xc6vlx760-ff1760-2.ngd ; sleep 10
map -intstyle silent -ol high -mt on -detail -o test_xc6vlx760-ff1760-2_map.ncd test_xc6vlx760-ff1760-2.ngd ; sleep 10
par -intstyle silent -ol high test_xc6vlx760-ff1760-2_map.ncd test_xc6vlx760-ff1760-2_par.ncd ; sleep 10
trce -a -nodatasheet -v 30 test_xc6vlx760-ff1760-2_par.ncd ; touch finished_all.mark
Generally, to run the script, the steps consist of:
Create a folder and move the entire extracted folder "test" into this newly created folder.
Change the ".sh" into executable by typing "chmod 777 test_xc6vlx760-ff1760-2". After this, you can use "ls" command to check whether this shell script is executable.
Type "./test_xc6vlx760-ff1760-2.sh". Keep your finger crossed and wait for the place-and-route report.
Today, the design on FPGA usually requires more than just getting a few reports. For example, we may want to use other GUI such as PlanAhead tool to examine the critical paths and retime the registers. The above scripting technique, however, gives you a faster way to estimate the performance. Again, the new Vivado design suite is much faster in this sense. That is probably the reason why our entire group is no longer using ISE.
For more information, please refer to the Xilinx XST User Guide.