A good RTL designer has to know the difference between a synchronous reset and an asynchronous reset.
Synchronous reset:
always@(posedge clk)
begin
if (rst) ...
What are the advantages of a synchronous reset? The use of a synchronous reset means the entire design is 100% synchronous. Timing is relatively easy in this case. The reset will be glitch-free as well. If reset is generated inside the system, then it is most likely to be a synchronous reset. However, a synchronous reset requires the pulse width to be long enough to reset the system (3~4 clock cycles in real logic designs). Sometimes this is quite annoying.
Asynchronous reset:
always@(posedge clk, posedge rst)
begin
if (rst) ...
The asynchronous reset leads to a clean data path, and no clock is required to assert the reset signal. If reset is provided outside the system (such as a reset button), then it is likely to be this type. From DFT's point of view, asynchronous reset is difficult to debug, since it is not easy to control the internal reset signals. The timing is difficult; remember that releasing a reset can lead to metastability. Glitches on an asynchronous reset can trigger false alarms.
For synchronous reset, both its rising and falling edges have to be kept away from the clock edge; this is straightforward if the reset signals are generated internally. For asynchronous reset, only the releasing edge has to be kept away; however, in most cases, this is not easily guaranteed, so we need to synchronize the reset.
The setup time for a reset signal is called reset recovery time.
In a system with multiple clock domains, reset is asserted or deasserted in 2 ways: either (1) using handshake signals, or (2) ordering the sequence of the reset signals.