Blog
08/09/2021 Maximum Alternating Subsequence Sum
08/02/2021 Embedded System Interview Questions (4)
08/01/2021 Embedded System Interview Questions (3)
07/31/2021 Embedded System Interview Questions (2)
07/30/2021 Embedded System Interview Questions (1)
07/23/2021 Number of Longest Increasing Subsequence
08/24/2020 Copying Hierarchical Design in Vivado
08/08/2020 GPIO Programming on Embedded Linux
07/08/2019 SWIG for Python C Binding
06/26/2019 Modify Petalinux Device Tree
01/28/2019 Monitor Python class attributes (3)
01/27/2019 Monitor Python class attributes (2)
01/26/2019 Monitor Python class attributes (1)
01/16/2019 Program FPGA in U-boot
01/10/2019 Partial Reconfiguration on Vivado 2018.3
10/24/2018 Error Handling in Makefile
10/23/2018 Use Vagrant to Configure VM
06/14/2018 Working with Oracle Java Environment
11/17/2017 Packaging Vivado IP
11/16/2017 Adding UIO into ZYNQ Devicetree
11/11/2017 GitHub Tricks - Splitting Commits
11/10/2017 GitHub Tricks - Submodule
06/28/2017 Python: Singleton (2)
06/21/2017 Python: Singleton (1)
04/07/2017 Python: List, Dictionary, or Array?
04/06/2017 Python: How to Construct a Bit Mask?
09/19/2016 Performance of Matrix Multiplication
03/21/2016 Bitstream Reconfiguration (Linux)
01/06/2016 Adding Boards to Vivado
12/14/2015 Copying a Batch of Files
12/02/2015 Bitstream Reconfiguration (Bare-metal)
10/19/2015 ARM Linker Script and Assemblies
10/16/2015 Using Interrupts in Embedded Systems
10/08/2015 Taking Seats on a Plane
10/05/2015 Reset: Synchronous vs. Asynchronous
10/04/2015 Conditional Probability
10/02/2015 Interview Questions (3)
10/01/2015 Interview Questions (2)
09/30/2015 Interview Questions (1)
09/29/2015 Crossing Clock Domains - Gray Codes
09/28/2015 Verilog "Case" Statement
09/27/2015 Crossing Clock Domains - Synchronizer
09/26/2015 Synchronization of RESET
05/28/2015 Running Xilinx ISE Scripts