Ace the Interview
September 25, 2015
Most of the EE students are very interested in getting a job in ASIC design space, either front-end or back-end. RTL coding as well as backend layout does not seem boring for these people (and for me as well). First, although it does require a remarkable time to become a RTL expert, Verilog and VHDL codes are easier to understand and debug at the first glance. Second, the tedious layout work looks very similar as drawing your own picture on a piece of canvas, which is full of design tricks.
However, it is now getting even harder for EE students to get a job in this area. The reasons include:
The ASIC design itself is full of risks everywhere. Anything can go wrong, with the loss easily up to millions of dollars. Hardware designers have to be very clear what they are doing while keeping everything into consideration. Experience is always a good thing. This is what matters: new graduates don't have so much experience!
To make thinks worse, EE has become more stabilized nowadays. There are only a few prestigious companies out there and too many experienced engineers (already!) in this industry. Despite this fact, there are also ASIC companies constantly laying off people (you name it). This makes life even harder.
Maybe you can argue we can go for FPGA instead of ASIC. FPGA offers reconfigurability so "maybe" your design tolerate some bugs, since you can always reconfigure the device. The problem is, however, FPGA industry has less consumers than ASIC. For Xilinx, as an example, the revenue becomes stabilized for years; it had to go for MPSoC to look for potentially more customers. Everyone knows what is going to happen to Altera. If FPGA companies don't grow anymore, what makes you think new graduates can easily get jobs as FPGA design engineers?
I think you must be already terrified by the situation. These are still not the points I am making, though.
The most important factor, is the design complexity. I know people like ASIC because of its high performance; however, ASIC is not a panacea for all the electronic devices due to its complexity. The developing period is too long. As the design goes bigger, it involves more and more engineers at more cost. Too many things can go wrong.
So there is another transition, which is the major take-away from this blog: hardware abstraction. You probably don't know what this is, but you probably heard or used some of the tools: HLS, OpenCL, SDSoC, etc. This concept is saying we can use high-level language to describe behavior of hardware, which frees the engineers from thinking about all the hardware components, drivers, kernels, etc. I recommend every hardware design engineers to master some software programming skills to adapt to the future changes. You won't regret it.
If you still think RTL design is your life, and you don't want to do any of the software programming, then first ask some questions such as "can I answer all the questions listed in the following pages?".
There are probably more sources you can read, but these two are definitely some you should never miss. For example, do you know how to use "case" in Verilog? How do you efficiently write a 1-hot state machine will parallel case statement? Do you know the ways to cross clock domains?
If you cannot answer both of the above questions within 1 min, then probably you won't get the offer. The real questions, can be much more difficult than what I mentioned here. Please read the two websites I listed carefully (yes, every single article and every single post!).
Besides the basic design techniques, let me ask some basic questions on computer architecture:
Do you know why we need Tomasulo algorithm? (if your answer does not talk about ILP, then you are on the wrong track.)
Can you draw the organization of a computer? (Missing any part means you will be shot down in the interview.)
Okay, let us stop here since there are too many pieces of information. I would probably continue along this line based on my schedule. Once in EE, you will have to keep learning as the technologies advance!