September 26, 2015

Perhaps many people don't understand this concept, unless you are really in this field. Let me start with the basic question as follows: You have a system purely synchronized to a clock signal "clock". The system has to be reset at some point. Let us consider the following cases:

1. The reset is asserted; all the output signals have been reset to logical "0". This step does not have to be synchronized to the "clock". The reason is easy: If you want to make all the outputs invalid anyway, why do you care what outputs you will be generating?

2. The reset is deasserted. Now the timing becomes very important. Suppose you have thousands of registers, how do you make sure all of them start to generate the right result exactly at the same time? For example, if you use a push button to trigger the reset, how do you make sure the release of the reset does not violate the setup time of all the registers? Note this is very important due to metastability!

Now let me show the graph on the right side and introduce why it works. When the reset is asserted, although both of the 2 registers are asynchronously reset, this does not matter because we don't care about the output in this case. When the reset is deasserted, we use the clock signal to double-sample a logic constant ("1" in this case). The use of 2 registers can help eliminate metastability on "rst1". The reason is the same as clock domain crossing: we want stable values in the worst case, even if they are delayed, rather than scrambled values!

The RTL code is very easy to write. Try to beat me in terms of lines of codes:

always@(posedge clock)

if (rst) {q_tmp, rst2_n} <=2'b0;

else {rst2_n, q_tmp} <= {q_tmp, 1'b1};

Now except the polarity of the reset signal, we have a second reset signal "rst2_n" perfectly synchronized with the clock signal.