Today I will cover questions regarding computer architectures, such as micro-controller, micro-processor, ARM, etc.
CISC vs RISC
The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible.
RISC processors only use simple instructions that can be executed within one clock cycle.
Harvard vs Von Neuman Architecture
In a Von-Neumann architecture, the same memory and bus are used to store both data and instructions that run the program; while in Harvard architecture, they are separated.
Flynn’s Taxonomy
SISD, SIMD, MISD, MIMD
DMA vs Polling vs Interrupts
Direct memory access sends data between computational units and memory without intervention from CPU
In polling mode, CPU constantly checks the status of the device
In interrupt mode, CPU is only informed by device once the task is done
I/O mapped I/O vs Memory Mapped I/O
In I/O mapped I/O, memory and I/O have separate address spaces while in memory-mapped I/O they share the same address space.
Virtual Memory
Virtual memory is a memory management technique where secondary memory can be used as if it were a part of the main memory.
Pipeline
An architecture that allows instructions to be processed in parallel.
Instruction Level Parallelism, Thread Level Parallelism.
ILP exploits the hardware, usually pipeline, to achieve parallelism.
TLP exploits the software, like many threads, to achieve parallelism.
Superscalar Architecture, VLIW Architecture, EPIC Architecture, SMT and Multi-core
A superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor.
VLIW (Very Long Instruction Word) has very wide instructions that offers large amounts of irregular instruction-level parallelism (ILP) by overlapping the execution of multiple machine-level operations within a single flow of control.
Explicitly Parallel Instruction Computing (EPIC) refers to architectures in which features are provided to facilitate compiler enhancements of instruction-level parallelism (ILP) in all programs.
Simultaneous multithreading (SMT) is a technique for improving the overall efficiency of superscalar CPUs with hardware multithreading.
Multicore refers to an architecture in which a single physical processor incorporates the core logic of more than one processor.
RAM Vs ROM
Random Access Memory that allows read and write.
Read Only Memory only supports write.
Various Addressing modes in 8086
The addressing modes provided by the 8086 family include displacement-only, base, displacement plus base, base plus indexed, and displacement plus base plus indexed. Variations on these five forms provide the 17 different addressing modes on the 8086.
What are interrupts? Types of interrupts?
Signaling mechanism that interrupts the CPU for higher-priority tasks.
Hardware/software, edge-triggered/level-triggered, etc.
What is ISR?
Interrupt Service Routine, also called an interrupt handler, is a software process invoked by an interrupt request from a hardware device. It handles the request and sends it to the CPU, interrupting the active process. When the ISR is complete, the process is resumed.
What is return type of ISR?
ISR does not return anything.
Can we use any function inside ISR?
You can call a function from an ISR if it is only the ISR that is calling the function. Some compilers will flag an error if an ISR calls a function that is also called from another part of the program.
Can we use printf inside ISR?
Generally, we don’t want to use printf, since it's not valid for reentrant, also ISR is supposed to be short, but printf takes too much time.
Can we put breakpoint inside ISR?
We can only set breakpoint in emulator where hardware is emulated. Since during the process of ISR, it will occupy the CPU resource.
What is interrupt latency?
Interrupt latency is the time that elapses from when an interrupt is generated to when the source of the interrupt is serviced.
Types of Cache mapping.
Direct, fully-associative, set-associative.
What is Snooping Cache?
Snooping maintains the consistency of caches in a multiprocessor. The snooping unit uses a MESI-style cache coherency protocol that categorizes each cache line as either modified, exclusive, shared, or invalid.
Watchdog Timer.
A watchdog timer provides automatic detection of catastrophic malfunctions that prevent the computer from kicking it.
Brown out Reset (COP Timer), Power-On Reset
A brownout is an intentional or unintentional drop in voltage in an electrical power supply system.
Power-on reset is the reset signal provided once the board is powered.
DRAM/ SDRAM Controller
1 transistor per cell vs 6 transistors per cell. DRAM requires refresh and quite a bit of initialization sequences once powered.
e-Flash Controller
A flash memory controller (or flash controller) manages data stored on flash memory and communicates with a computer or electronic device.
Interrupt Controller
An interrupt controller provides a programmable governing policy that allows software to determine which peripheral or device can interrupt the processor at any specific time by setting the appropriate bits in the interrupt controller registers.
Timers
A device or software program that counts down from a specified time interval and used to generate a time delay.
DMA Controller
A DMA controller can generate memory addresses and initiate memory read or write cycles. It contains several hardware registers that can be written and read by the CPU.