Aug 24, 2020

For FPGA design engineers using Vivado, there is an old quick trick to move hierarchical design onto a different block design. I would really like to go over this trick again in this blog.

The original problem looks like this: suppose you have a nice block design already built in Vivado, and there happens to be a nice hierarchical block in that design that you want to reuse, and you want to 'copy-and-paste' that hierarchical design onto a brand-new block design in Vivado. However, 'copy-and-paste' does not work across different Vivado windows so there is no straight-forward way to port your design over.

This looks annoying at the first glance but it is not that hard if you know the following trick:

Step 1: Export you design into tcl file

Suppose you have a hierarchical block called 'block_to_export' in the top-level of your original block design. In Vivado tcl command window, use the following command to generate the tcl file:

write_bd_tcl -hier_blks [get_bd_cells /block_to_export] ./exported_block.tcl

This will generate a tcl file called 'exported_block.tcl' in your current working directory.

Step 2: Source the generated tcl file in your new project

Move the 'exported_block.tcl' into your new project folder and source it:

source exported_block.tcl

This will make your hierarchical block available to your new block design. You can also see some instructions in Vivado tcl command window on how to reference the hierarchical block 'block_to_export'.

Step 3: Source the generated tcl file in your new project

To be more specific on how to reference the hierarchical block, let's say you want to hierarchical block to be named as 'name_for_block'. Then you can do:

create_hier_cell_block_to_export [current_bd_instance .] name_for_block

Now you should be able to see the hierarchical block appears in your new block design!