Wook Hyun Kwon, South Korean electrical engineer (19 January 1943 –
Authored over 150 international journal papers
Introduced the concept of receding horizon control
A modified quadratic cost problem and feedback stabilization of linear systems. IEEE Trans. Autom. Control Vol AC 22(5), 1977
First to introduce a reduction transformation method for control-delayed systems
With A.E. Pearson. Feedback stabilization of linear systems with delayed control. IEEE Trans. Autom. Control Vol AC 25(2), 1990
Introduced for the first time a H-infinity control method for time-delay systems
With J.H. Lee & S.W. Kim. Memoryless H controllers for state delayed systems. IEEE Trans. 39(1), 1994
Introduced a very useful and powerful inequality equation for robust stabilizing controls for time delay systems
With Y.S. Moon, P.G. Park & Y.S. Lee. Delay dependent robust stabilization of uncertain state-delayed systems. Intern. J. Control 74(14), 2001
PATENTS (24 patents in South Korea)
With M.K. Cho & E.S. Cho. Non-volatile memory devices that include a section transistor having a recessed channel and methods of fabricating the same. USPTO 20060023558
With J.I. Han. Selective erase method for flash memory USPTO 20060018163
With K.Y. Na. Non-volatile memory device and fabrication method USPTO 6849506 (2003)
With K.Y. Na. Non-volatile memory device and fabrication method USPTO 20040048432
With K.Y. Na. Non-volatile memory device and fabrication method USPTO 20020017680
With K.Y. Na. Non-volatile memory device with a floating gate having a tapered protrusion USPTO 6649967 (2001)
With K.Y. Na, S.B. Lee, Y.H. Kim & W.L. Choi. Method for fabricating connection between segment transistor and memory cell region of flash memory device. USPTO 6566197 (2001)
With K.Y.Na, S.B. Lee, Y.H. Kim & W.L. Choi. Method for fabricating connection structure between segment transistor and memory cell region of flash memory device USPTO 20020025635
Nonvolatile memory, cell array thereof, and method for sensing data therefrom USPTO 20030002335
Nonvolatile memory, cell array thereof, and method for sensing data therefrom USPTO 6501680 (2002)
Nonvolatile memory, cell array thereof, and method for sensing data therefrom USPTO 6438027 (2001)
Nonvolatile memory, cell array thereof, and method for sensing data therefrom USPTO 20020060337
Nonvolatile memory, cell array thereof, and method for sensing data therefrom USPTO 6313501 (2000)
Fabrication method of triple polysilicon flash eeprom arrays USPTO 6218246
With G.B. Lee, K.S. Kim, S.A. Nam & N.J. Son. Method of manufacturating semiconductor device USPTO 9564340 (2015)
With G.B. Lee, K.S. Kim, S.A. Nam & N.J. Son. Method of manufacturating semiconductor device USPTO 20160225635
With B.G. Park, Y.H. Song & Y. Kim. Methods of forming and operating semiconductor device. USPTO 8354708 (2011)
With B.G. Park, Y.H. Song & Y. Kim. Methods of forming and operating semiconductor device. USPTO 20110194356
Non-volatile memories, cards, and systems including shallow trench isolation structures with buried bit lines. USPTO 20110302363
Methods of forming shallow trench isolation structures with buried bit lines in non-volatile memories. USPTO 8022462 (2008)
With B.G. Park, Y.H. Song & Y. Kim. Semiconductor device and methods of forming and operating the same. USPTO 7928501 (2009)
With B.G. Park, Y.H. Song & Y. Kim. Methods of forming and operating semiconductor device. USPTO 20100001339
With K.N. Kim, C.K. Park, S.M. Jung & S.P. Sim. Multilevel integrated devices and methods of forming the same USPTO 7586135 (2006)
With M.K. Cho & E.S. Cho. Non-volatile memory devices that include a selection transistor having a recessed channel and methods of fabricating the same USPTO 7547943 (2004)
Non-volatile memory device capable of reducing threshold voltage distribution USPTO 7468924 (2006)
Non-volatile memory device capable of reducing threshold voltage distribution USPTO 20080094923 (2006)
Methods of forming shallow trench isolation structures with buried bit lines in non-volatile memories and devices, cards, and systems so formed USPTO 20080265303 (2008)
Methods of forming non-volatile memory device having floating gate USPTO 7338860 (2005)
Methods of forming non-volatile memory device having floating gate USPTO 20060099756
With D.M. Kim, K.N. Kim, C.K. Park & S.P. Sim. Methods for operating non-volatile memory device USPTO 20070268749
With C.K. Park & S.P. Sim. Contatcless nonvolatile memory device and method of forming the same. USPTO 7276415 (2006)
With C.K. Park & S.P. Sim. Contatcless nonvolatile memory device and method of forming the same. USPTO 20070105309
With K.N. Kim, C.K. Park, S.M. Jung & S.P. Sim. Multilevel integrated circuit devices and methods of forming the same USPTO 20070176214
With J.I. Han. Selective erase method for flash memory. USPTO 7230853
LINKS
https://kwonlecture.snu.ac.kr/wp-content/uploads/2018/01/CV-of-Prof-kwon-16-12-21short.pdf