Suppose we have a UART with a baud rate of 9,600 bits/sec and a counter clock frequency of 3 MHz. The division factor in this case is N = 3 MHz / 9600 = 312.5. To sample the start bit after the falling edge, we have to count up to half of N only (half a cycle). This is 156.25. Notice that neither N, nor its half are integers. However, the timer counter can only accept an integer as its value. We have a choice between using 156 and 157 for the start bit. After we sample the start bit, we have to choose between 312 and 313.

The length of each baud is ideally 1/9600 ≈ 104.17 µs. If we choose the lower values,  312, then sampling will occur every 312 / 3 MHz = 104 µs, which is 0.17 µs less than the ideal sampling time. Eventually, over a long time, the error will accumulate such that the same bit can get sampled more than once (which leads to inaccurate data). If we choose 313, then sampling will occur every 313 / 3 MHz ≈ 104.33 µs, which is ~0.16 µs more than the ideal sampling time. Eventually, over a long time, the error will accumulate such that one bit may not get sampled at all (which also leads to inaccurate data).

In either case, the error accumulates, which eventually leads to data corruption. The solution to this predicament is to use modulation, which is oscillating between the two values such that the error accumulation “cancels out.” 

Even with modulation, there is still some error, which can be attributed to the approximations that are made. Nonetheless, the error is so small that with small data frames, it is guaranteed that no error occurs during sampling, at least due to sampling time.

The division factor is comprised of an integer part plus a fractional part. For this example, the division factor had an integer part of 312 and a fractional part of 0.5. Because the fractional part happened to be 0.5, so we could easily alternate between 312 and 313 every cycle (or in other words, the counter value was 312 one-half of the time and 313 for the other half). If the fractional part was instead 0.25, we could instead use 312 three times and then 313 one time (so 312 is used ¾ of the time and 313 was used ¼ of the time) in the following pattern: 312, 312, 312, 313, 312, 312,312, 313. This sequence keeps the sampling times close to the center of the cycle as possible.

The following spreadsheet shows the mechanics of how ideal and actual sampling times differ from each other under three scenarios: fast sampling when we use the floor of the division factor, slow sampling when we use the ceiling of the division factor, and finally modulation when we oscillate between the floor and the ceiling. 

Make sure to click on all the tabs to see different scenarios. In each tab, the green cells show the ideal sampling times for each bit that is right in the middle of the baud symbol. In other words, the ideal time is the middle of the bit cycle. For each tab, the pink cells show the process of calculating and actual sampling time. Note that the real sampling time is based on the value we put in the counter. If we always choose the ceiling of the division factor in the counter, we are sampling too slow, and the error, which is the difference between ideal and actual time keeps increasing. If we always choose the floor of the division factor, we are always too fast. The third tab, sampling with modulation, shows when we switch between the floor and ceiling. The pattern bits in the pattern column decide whether we are using the floor or the ceiling. Make sure to click on the last tab that shows the error comparison for all three scenarios. 

The next spreadsheet is very similar to the previous one except that the baudrate is 19200 bps instead of 9600. The division factor is 156.25. If we use the same pattern of 01010101 and switch back and forth between 156 and 157, we will see that the error still accumulates to an extent. Since 156.25 is closer to 156 than 157, we use 156 more often than 157. So, we use the pattern 00010001 where we use 156 three times, followed by one 157, and then, we go back to another 156, and so on. 

For factional values such as 0.5 and 0.25, it is easy to guess what the pattern should be. What happens if we encounter a fractional part such as 0.1415 or 0.7331? Luckily, the technical manual contains a table for looking up these modulation patterns. To ascertain the modulation pattern of a division factor, find the two values in the “Fractional Portion of N” column that the fractional part of your division factor falls between. If it is exactly equivalent to one of those two values, then choose the corresponding UCBRSx value. Otherwise, choose the lower of the two values. Notice that the UCBRSx value is in hexadecimal. If you expanded it out to a binary number, you will get the modulation pattern for sampling eight bits.

For example, a division factor of 79.787 will have a modulation pattern of 0xED, which expands to 11101101. Every time you see a 0, use the integer part of the division factor. Every time you see a 1, use the integer part plus one. So the counter values would follow a pattern of: 80, 80, 80, 79, 80, 80, 79, 80.